Patents by Inventor Richard J. Casabona

Richard J. Casabona has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5175613
    Abstract: A package for integrated circuit chips, or other electrical devices, provides mechanical shock and thermal protection for the chips, and in addition, protects the chips from electromagnetic interference and electrostatic discharge. The package includes a printed wiring board base for reception of one or more circuit chips, and a conductive heat sink and cover. The conductive heat sink, in conjunction with a reference plane in the wiring board base, acts as an EMI shield for the chips. The heat sink is covered with an insulating layer, on top of which, a conductive coating is placed. The conductive coating is electrically connected to the reference plane, and the two act to protect the chips from electrostatic discharges. Compliant pads support the chips, and a thermally conductive elastomer can be placed on top of each chip between the chips and the inner top surface of the heat sink. The chips are thereby held securely in position, and are thermally connected to the heat sink.
    Type: Grant
    Filed: January 18, 1991
    Date of Patent: December 29, 1992
    Assignee: Digital Equipment Corporation
    Inventors: Charles R. Barker, III, Richard J. Casabona, David M. Fenwick
  • Patent number: 4290102
    Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. Control is then relinquished unless the one element is to send data to the other element whereupon the data is sent immediately. If data is to be retrieved, the other element retrieves the data, requests control of the interconnection and, when it receives control, transmits the data onto the interconnection with an identification of the one element. The one element then retrieves the data from the interconnection when it recognizes its own identification.
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: September 15, 1981
    Assignee: Digital Equipment Corporation
    Inventors: John V. Levy, David Rodgers, Robert E. Stewart, Richard J. Casabona
  • Patent number: 4232366
    Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. Control is then relinquished unless the one element is to send data to the other element whereupon the data is sent immediately. If data is to be retrieved, the other element retrieves the data, requests control of the interconnection and, when it receives control, transmits the data onto the interconnection with an identification of the one element. The one element then retrieves the data from the interconnection when it recognizes its own identification.
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: November 4, 1980
    Assignee: Digital Equipment Corporation
    Inventors: John V. Levy, David P. Rodgers, Robert E. Stewart, Richard J. Casabona
  • Patent number: 4229791
    Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: October 21, 1980
    Assignee: Digital Equipment Corporation
    Inventors: John V. Levy, David Rodgers, Robert E. Stewart, David Potter, Richard J. Casabona