Patents by Inventor Richard Joseph Saia

Richard Joseph Saia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090028491
    Abstract: An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a sur
    Type: Application
    Filed: July 26, 2007
    Publication date: January 29, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Raymond Albert Fillion, Kevin Matthew Durocher, Richard Joseph Saia, Charles Gerard Woychik
  • Patent number: 6994897
    Abstract: A mechanism and a method for framing a low-distortion flexible dielectric substrate during subsequent flex circuit processing. The processing method comprising the following steps: making a flexible dielectric substrate having an outer periphery; joining a continuous portion of the flexible dielectric substrate near the outer periphery to a rigid open frame, the flexible dielectric substrate being in a state other than a state of substantially uniform tension as a result of the joinder; causing the joined flexible dielectric substrate to undergo a change to the state of substantially uniform tension; and printing an electrical conductor on the flexible dielectric substrate while the flexible dielectric substrate is joined to the frame and in the state of substantially uniform tension. The frame is in the shape of a polygon (e.g., a rectangle) with rounded vertices.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: February 7, 2006
    Assignee: General Electric Company
    Inventors: Kevin Matthew Durocher, Christopher James Kapusta, Mehmet Arik, Richard Joseph Saia, Piet Moeleker
  • Patent number: 6988706
    Abstract: A piezoelectric microvalve and method for controlling a fluid flow through a piezoelectric microvalve are provided. The microvalve includes an inlet plenum and a flow directing structure for directing a fluid flow, wherein a first side of the structure is in fluid communication with the inlet plenum. The microvalve also includes a piezoelectric bending actuator comprising a flap portion responsive to a command signal for controlling a fluid flow through the flow directing structure. The microvalve further includes an outlet plenum in fluid communication with a second side of the flow directing structure.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 24, 2006
    Assignee: General Electric Company
    Inventors: Charles Erklin Seeley, Richard Joseph Saia, Christopher James Kapusta, David Joseph Najewicz, Anis Zribi, Guanghua (George) Wu
  • Patent number: 6935792
    Abstract: An optoelectronic package is fabricated by a method which includes: positioning an optical device within a window of a substrate active-side up and below a top substrate surface; filling the window with an optical polymer material; planarizing surfaces of the optical polymer material and the substrate; patterning waveguide material over the optical polymer material and the substrate to form an optical interconnection path; and to form a mirror to reflect light from the optical device to the interconnection path; and forming a via to expose a bond pad of the optical device.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: August 30, 2005
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Thomas Bert Gorczyca, Christopher James Kapusta, Ernest Wayne Balch, Glenn Scott Claydon, Samhita Dasgupta, Eladio Clemente Delgado
  • Patent number: 6790703
    Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 14, 2004
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose, Leonard Richard Douglas
  • Patent number: 6773962
    Abstract: A method for packaging a microelectromechanical system (MEMS) device comprises: using a partially-cured adhesive to attach a release sheet to a MEMS package flexible layer; providing a cavity extending through the release sheet and at least partially through the MEMS package flexible layer; removing the release sheet; and attaching the MEMS device to the MEMS package flexible layer with a MEMS structure of the MEMS device being positioned within the cavity.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: August 10, 2004
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, Christopher James Kapusta, Matthew Christian Nielsen
  • Patent number: 6767764
    Abstract: A method for packaging a microelectromechanical system (MEMS) device comprises: using a partially-cured adhesive to attach a release sheet to a MEMS package flexible layer; providing a cavity extending through the release sheet and at least partially through the MEMS package flexible layer; removing the release sheet; and attaching the MEMS device to the MEMS package flexible layer with a MEMS structure of the MEMS device being positioned within the cavity.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: July 27, 2004
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, Christopher James Kapusta, Matthew Christian Nielsen
  • Publication number: 20040094329
    Abstract: A mechanism and a method for framing a low-distortion flexible dielectric substrate during subsequent flex circuit processing. The processing method comprising the following steps: making a flexible dielectric substrate having an outer periphery; joining a continuous portion of the flexible dielectric substrate near the outer periphery to a rigid open frame, the flexible dielectric substrate being in a state other than a state of substantially uniform tension as a result of the joinder; causing the joined flexible dielectric substrate to undergo a change to the state of substantially uniform tension; and printing an electrical conductor on the flexible dielectric substrate while the flexible dielectric substrate is joined to the frame and in the state of substantially uniform tension. The frame is in the shape of a polygon (e.g., a rectangle) with rounded vertices.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventors: Kevin Matthew Durocher, Christopher James Kapusta, Mehmet Arik, Richard Joseph Saia, Piet Moeleker
  • Patent number: 6733711
    Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: May 11, 2004
    Assignee: General Electric Company
    Inventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
  • Patent number: 6730533
    Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: May 4, 2004
    Assignee: General Electric Company
    Inventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
  • Publication number: 20040076382
    Abstract: An optoelectronic package is fabricated by a method which includes: positioning an optical device within a window of a substrate active-side up and below a top substrate surface; filling the window with an optical polymer material; planarizing surfaces of the optical polymer material and the substrate; patterning waveguide material over the optical polymer material and the substrate to form an optical interconnection path and to form a mirror to reflect light from the optical device to the interconnection path; and forming a via to expose a bond pad of the optical device.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Applicant: General Electric Company
    Inventors: Richard Joseph Saia, Thomas Bert Gorczyca, Christopher James Kapusta, Ernest Wayne Balch, Glenn Scott Claydon, Samhita Dasgupta, Eladio Clemente Delgado
  • Patent number: 6614103
    Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: September 2, 2003
    Assignee: General Electric Company
    Inventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
  • Publication number: 20030160256
    Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
    Type: Application
    Filed: March 14, 2003
    Publication date: August 28, 2003
    Applicant: General Electric Company
    Inventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
  • Patent number: 6548329
    Abstract: A hard layer of amorphous hydrogenated carbon (DLC) overlies a polymer film structure and a plurality of soft layers of DLC alternate with a plurality of hard layers of DLC over the barrier base to form a corrosion resistant structure. The polymer film structure and a circuit chip can be elements of a circuit module. The DLC and the polymer film structure can have vias extending to contact pads, and a pattern of electrical conductors can extend through the vias to the contact pads. In one embodiment the DLC forms a hermetic (and therefore corrosion resistant) seal over the polymer film structure.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: April 15, 2003
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose
  • Patent number: 6515417
    Abstract: The invention relates to a light source comprising one or more organic light emitting devices mounted on a mounting substrate, each of the organic light emitting devices comprising a first electrode which is light transmissive, an organic light emitting layer, a second electrode, a first device electrical contact extending from the first electrode to the mounting substrate, and a second device electrical contact extending from the second electrode to the mounting substrate. The invention also relates to a method of making such a light source.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: February 4, 2003
    Assignee: General Electric Company
    Inventors: Anil Raj Duggal, Richard Joseph Saia, Paul Alan McConnelee, Larry Gene Turner
  • Publication number: 20020197767
    Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.
    Type: Application
    Filed: July 22, 2002
    Publication date: December 26, 2002
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose, Leonard Richard Douglas
  • Publication number: 20020173080
    Abstract: A method for packaging a microelectromechanical system (MEMS) device comprises: using a partially-cured adhesive to attach a release sheet to a MEMS package flexible layer; providing a cavity extending through the release sheet and at least partially through the MEMS package flexible layer; removing the release sheet; and attaching the MEMS device to the MEMS package flexible layer with a MEMS structure of the MEMS device being positioned within the cavity.
    Type: Application
    Filed: June 12, 2002
    Publication date: November 21, 2002
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, Christopher James Kapusta, Matthew Christian Nielsen
  • Patent number: 6475877
    Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: November 5, 2002
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, James Wilson Rose, Leonard Richard Douglas
  • Publication number: 20020132391
    Abstract: A method for packaging a microelectromechanical system (MEMS) device comprises: using a partially-cured adhesive to attach a release sheet to a MEMS package flexible layer; providing a cavity extending through the release sheet and at least partially through the MEMS package flexible layer; removing the release sheet; and attaching the MEMS device to the MEMS package flexible layer with a MEMS structure of the MEMS device being positioned within the cavity.
    Type: Application
    Filed: March 15, 2001
    Publication date: September 19, 2002
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, Christopher James Kapusta, Matthew Christian Nielsen
  • Patent number: 6429381
    Abstract: A method for fabricating a substrate package for a high density interconnect multichip module stack comprises: providing a substrate having holes extending therethrough and having a bottom surface with metallization situated thereon; providing a metal sheet having grooves extending therethrough; attaching the metal sheet to the bottom surface of the substrate; attaching metal plugs through the holes to the metal sheet; and removing portions of the substrate to expose the metal plugs and separate the metal sheet into a plurality of segments defined by the grooves.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: August 6, 2002
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Robert John Wojnarowski, Stanton Earl Weaver, Jr., Kevin Matthew Durocher, Christopher James Kapusta, James Enrico Sabatini