Patents by Inventor Richard Kaltenbach

Richard Kaltenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shadow pointer directory in an inclusive hierarchical cache
    Patent number: 11977486
    Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: May 7, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashraf ElSharif, Richard Joseph Branciforte, Gregory William Alexander, Deanna Postles Dunn Berger, Timothy Bronson, Aaron Tsai, Taylor J. Pritchard, Markus Kaltenbach, Christian Jacobi, Michael A. Blake
  • System power management using memory throttle signal
    Patent number: 8549329
    Abstract: According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory throttling signal will be asserted and/or that a processor power control signal will be asserted.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventors: Gopal Mundada, Xiuting (Kaleen) Man, Brian Griffith, Viktor D. Vogman, Richard Kaltenbach
  • SYSTEM POWER MANAGEMENT USING MEMORY THROTTLE SIGNAL
    Publication number: 20100169690
    Abstract: According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory throttling signal will be asserted and/or that a processor power control signal will be asserted.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Gopal Mundada, Xiuting (Kaleen) Man, Brian Griffith, Viktor D. Vogman, Richard Kaltenbach