Patents by Inventor Richard Klass

Richard Klass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126702
    Abstract: Techniques for slicing memory of a hardware processor core by linear address are described.
    Type: Application
    Filed: September 21, 2022
    Publication date: April 18, 2024
    Inventors: Mark Dechene, Ryan Carlson, Sudeepto Majumdar, Rafael Trapani Possignolo, Paula Petrica, Richard Klass, Meenakshi Marathe
  • Publication number: 20240037036
    Abstract: Techniques for scheduling merged store operations are described. In an embodiment, an apparatus includes a data cache; a fill buffer; a store buffer to store first information associated with a first retired store operation and second information associated with a second retired store operation; a store coalescing buffer (SCB) to receive the first information from the store buffer, to store the first information in an SCB entry, to merge the second information from the store buffer into the entry, and to provide data associated with the entry for a write to the data cache or the fill buffer; and a global store scheduler (GSS) to schedule the write relative to an other write from an other SCB in compliance with one or more store ordering rules.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: Intel Corporation
    Inventors: Mark Dechene, Ryan Carlson, Ricardo Daniel Queiros Alves, Yan Zeng, Richard Klass, Brendan West
  • Publication number: 20060075192
    Abstract: In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Inventors: Michael Golden, Richard Klass
  • Patent number: 5281809
    Abstract: A method of operation of a light curtain system for sensing the intrusion of objects into detection planes which define a protected zone. A group of light beams are strobed from one transmitter in a first direction across a zone to a receiver, and another group of light beams are strobed from another transmitter across the zone to another receiver. Light beams within each group which intersect a desired entry area are deactivated for penetration of a permitted object, and other beams in the groups are enabled to detect intrusion into the objects in portions of the zone which lie around the entry area.
    Type: Grant
    Filed: December 22, 1992
    Date of Patent: January 25, 1994
    Assignee: Scientific Technologies Incorporated
    Inventors: E. Peter Anderson, James A. Ashford, Richard Klass
  • Patent number: 5198661
    Abstract: A light curtain system for sensing the intrusion of objects into detection planes which define a protected zone. A plurality of light curtain segments are provided with each segment including spaced-apart transmitter and receiver heads. The transmitter and receiver heads are each connected in series by flexible cables which form a part of a control circuit. The series-connected segments permit the detection planes to be aligned in predetermined angular orientations as required by the particular application.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: March 30, 1993
    Assignee: Scientific Technologies Incorporated
    Inventors: E. Peter Anderson, James A. Ashford, Richard Klass