Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.

Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.

Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively coupled to the hypervisor. The receive credit value to limit a first quantity of one or more first tasks in the first buffer. The hardware accelerator determines at least one memory address translation related to the operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation.

Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.

Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: A technique for handling cache-inhibited operations in a data processing system includes receiving, at a topology specific replicated bus unit, a cache-inhibited (CI) operation that is scope limited. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit, the replicated bus unit processes the CI operation based on the scope being limited to that of the replicated bus unit. In response to the address associated with the CI operation not matching the address for the replicated bus unit, the replicated bus unit ignores the CI operation.

Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The background counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.

Abstract: A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: A technique for handling interrupts in a data processing system includes maintaining, at an interrupt presentation controller (IPC), an interrupt acknowledge count (IAC). The IAC provides an indication of a number of times a virtual processor thread implemented at a first software stack level has been interrupted in response to receipt of event notification messages (ENMs) from an interrupt source controller (ISC). In response to the IAC reaching a threshold level, the IPC transmits an escalate message to the ISC. The escalate message includes an escalate event number that is used by the ISC to generate a new ENM that targets a second software stack level that is different than the first software stack level and is associated with another virtual processor thread.

Abstract: A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: A technique for escalating interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies a level, an event target number, a number of bits to ignore, and an event priority. A group of virtual processor threads that may be potentially interrupted is determined based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. In response to the event priority in the ENM not being greater than an operating priority of at least one virtual processor thread in the group of virtual processor threads, an escalate message that includes an escalate event number (EEN), sourced from an interrupt context table of the IPC, is issued. The EEN is used by an interrupt source controller to generate another ENM.

Abstract: A method of handling interrupts in a data processing system includes maintaining a first interrupt destination buffer (IDB) for a first interrupt handler routine (IHR) and a second IDB for a second IHR. Whether a received interrupt is associated with the first IHR or the second IHR is determined. In response to the received interrupt being associated with the first IHR, event information associated with the received interrupt is stored in the first IDB. In response to the received interrupt being associated with the second IHR, the event information associated with the received interrupt in stored in the second IDB.

Abstract: A technique for handling queued interrupts includes accumulating respective backlog counts for respective event paths. The background counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads. In response to a lowering of an operating priority (OP) of a VP thread (VPT), a scan backlog (SB) message is received that identifies the VPT and specifies a current operating priority for the VPT. In response to receiving the SB message, a linked list of event paths associated with the VPT is scanned to search for backlog events that have a higher priority than the current OP for the VPT. In response to a backlog event being located that has a higher priority than the current OP of the VPT, an interrupt to the VPT is initiated starting with a highest priority event path and the backlog count for the VPT is decremented.

Abstract: A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.

Abstract: A technique for handling cache-inhibited operations in a data processing system includes receiving, at a topology specific replicated bus unit, a cache-inhibited (CI) operation that is scope limited. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit, the replicated bus unit processes the CI operation based on the scope being limited to that of the replicated bus unit. In response to the address associated with the CI operation not matching the address for the replicated bus unit, the replicated bus unit ignores the CI operation.

Abstract: A technique for escalating interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies a level, an event target number, a number of bits to ignore, and an event priority. A group of virtual processor threads that may be potentially interrupted is determined based on the event target number, the number of bits to ignore, the level, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. In response to the event priority in the ENM not being greater than an operating priority of at least one virtual processor thread in the group of virtual processor threads, an escalate message that includes an escalate event number (EEN), sourced from an interrupt context table of the IPC, is issued. The EEN is used by an interrupt source controller to generate another ENM.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies an event target number, a number of bits to ignore, an event source number, and an event priority. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.