Abstract: Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master device—of a plurality of master devices coupled to a respective plurality of slave devices via an internal network—may implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.

Abstract: Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master device—of a plurality of master devices coupled to a respective plurality of slave devices via an internal network—may implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.

Abstract: A reduced cell library includes substantially fewer cells than a complete cell library used to finalize the integrated circuit design. More particularly, each cell in the reduced cell library may be characterized by a first drive strength which is the same for each cell in the library. The reduced cell library can be used to evaluate the RTL description of an integrated circuit without incurring long synthesis delays. Large problems in the RTL description (with respect to one or more design goals) may be detected, and the RTL description may be modified to correct the problems.

Abstract: A reduced cell library includes substantially fewer cells than a complete cell library used to finalize the integrated circuit design. Having fewer cells reduces the number of options available to the synthesis tool for realizing a particular RTL description. Hence, the amount of time elapsing during a synthesis run using the reduced cell library may be substantially shorter than a corresponding synthesis run using a complete cell library. The reduced cell library can be used to evaluate the RTL description of an integrated circuit without incurring long synthesis delays. Large problems in the RTL description (with respect to one or more design goals) may be detected, and the RTL description may be modified to correct the problems. Once the RTL description of the integrated circuit substantially meets the design goals of the integrated circuit using the reduced cell library, synthesis using the complete cell library is initiated.