Abstract: An operation of a processor is traced while fetching instructions from a memory to operate the processor. The tracing involves detecting an unpredictable fetching of instructions on the assumption that a predictable fetching can be reconstructed without any further input. The unpredictable fetching is identified as being due to either computable, conditional, or unanticipated events. Upon detecting the events, process control information, such as the next instruction to be fetched is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and the image including the instructions can be examined to analyze the real-time operation of the processor.

Abstract: In a computer system, an apparatus is configured to collect performance data of a computer system including a plurality of processors for concurrently executing instructions of a program. A plurality of performance counters are coupled to each processor. The performance counters store performance data generated by each processor while executing the instructions. An interrupt handler executes on each processors, the interrupt handler samples the performance data of the processor in response to interrupts. A first memory includes a hash table associated with each interrupt handler, the hash table stores the performance data sampled by the interrupt handler executing on the processor. A second memory includes an overflow buffer, the overflow buffer stores the performance data while portions of the hash tables are active or full. A third memory includes a user buffer, and means are provided for periodically flushing the performance data from the hash tables and the overflow to the user buffer.

Abstract: A data flow of a processor is traced while accessing data stored in a memory and in a plurality of registers during operation of the processor. The tracing involves detecting an unpredictable accessing of data on the assumption that a predictable accessing can be reconstructed without any further input. The unpredictable accessing is identified by setting and clearing a trace bit associated with each of the registers according to identifying the accessing as direct memory-to-register, register-to-register, constant-to-register, and indirect memory. If a trace bit is set on a register storing data being used as a base address during the indirect memory acceding, data flow control information, such as the base address stored in the register being used during the indirect acceding is recorded in a queue, and from the queue the information can be stored in a trace buffer.

Abstract: A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first instruction set and the second program code is executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set.A first computer translates the first code instructions to corresponding second code instructions in accordance with a pattern code that defines first code instructions in terms of second code instructions.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A program is translated by automatically generating a flowgraph, using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph, and then using the flowgraph and the information about the blocks of instructions to generate translated instructions. Due to execution transfers to computed destination addresses that are not determined prior to program execution, it is not possible to include all of the program instructions in the flowgraph. Execution transfers to these computed destinations are coded as calls to an interpreter that interprets the untranslated code. Returns from the interpreter are made to block entry points. Moreover, information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during re-translation of the original program.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.

Abstract: A system for evaluating the performance of a computer system having a processor that passes through a plurality of processor states during operation and an associated system memory includes an operating unit for receiving a request to monitor specific process states from a user. Firmware causes the processor to enter the desired processor state requested by the user. The hardware identifies the occurrence of the desired processor state. Information relating to the occurrence of the desired process state is accumulated the memory. The accumulated information is read from memory and a report is provided to the user.

Abstract: A code translator, constructed similar to a compiler, accepts as an input to be translated the assembly code written for one architecture (e.g., VAX), and produces as an output object code for a different machine architecture (e.g., RISC). The input code is converted into an intermediate language, and a flow graph is constructed. The flow graph is referenced by a flow analyzer for recognizing certain architecture-specific and calling standard-specific coding practices or idioms that can produce mistakes if not revised before converting, particularly relating to stack usage. By tracking stack usage within and across routines, the compiler can distinguish up-level stack and return address references from valid local references. Also, it can inform the user of stack misalignment, which has a severe performance penalty, and can detect code segments where different flow paths may result in different stack depths at runtime, which may indicate a source code error.

Abstract: A computer system using virtual memory addressing and having a direct-mapped cache is operated in a manner to simulate the effect of a set associative cache by detecting cache misses and remapping pages in the main memory so that memory references which would have caused thrashing can instead coexist in the cache. Two memory addresses which are in different pages but which map to the same location in the cache may not reside in the direct-mapped cache at the same time, so alternate reference to these addresses by a task executing on the CPU would cause thrashing. However, if the location of one of these addresses in main memory is changed, the data items having these addresses can coexist in the cache, and performance will be markedly improved because thrashing will no longer result. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain the same virtual address.

Abstract: Possible values for a computed destination address of an execution transfer instruction are found by a backward search through a flowgraph of a program. During the search, a symbolic expression for the destination address is successively modified to reflect the effect of each prior instruction until the symbolic expression represents an absolute or program-counter relative address, or until the search can no longer continue. The search can no longer continue, for example, when an instruction is reached that affects the value of the expression in an indefinite way. When backward symbolic execution reaches the entry point of a block in the flowgraph, backward symbolic execution proceeds backward to each predecessor block that has not already been examined for the execution transfer instruction. Therefore multiple definite values as well as a value of "unknown" may be found for a computed destination address.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: Information about the effects of calling each entry point in a program and information about external calls made by the program are recorded in an image information file. In addition to the addresses of the entry points and call destinations, the information may include any callback parameters and register usage associated with the entry points, and any definite values passed by the calls. When translating two separate but mutually dependent programs that are not easily merged for simultaneous translation, the image information files for the respective programs permit the programs to be alternately translated with rapid convergence by an iterative method of checked assumptions and re-translation.

Abstract: A computer program of complex instruction set code (CISC) is translated to produce a program of reduced instruction set code (RISC). Each CISC instruction is translated into a sequence of RISC instructions. The sequence includes in order four groups of instructions. The first group includes instructions that get inputs and place them in temporary storage. The second group includes instructions that operate on the inputs and place results in temporary storage. The third group includes instructions that update memory or register state and are subject to possible exceptions. The fourth group includes instructions that update memory or register state and are free of possible exceptions. When execution of the RISC program is interrupted by an asynchronous event, the RISC instruction being executed at the time of the interrupt is recorded and allowed to complete.

Abstract: Information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during re-translation of the original program. Preferably the information includes origin addresses of translated instructions and corresponding destination address of untranslated instructions of execution transfers that occur during the execution of the partial translation. Preferably this feedback of information from execution to re-translation is performed after each execution of the translated program so that virtually all of the instructions in the original program will eventually be located and translated. To provide an indication of the fraction of the code that has been translated, the program is scanned to find plausible code in the areas of memory that do not contain translated code.

Abstract: A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.

Abstract: A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table.

Abstract: A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.