Abstract: A framing template tool may include a face plate; a top plate joined to the face plate at about an edge thereof, wherein the top plate is substantially orthogonal to the face plate; and alignment features. The alignment features may include slots formed in the face plate along its length; and one or more flaps joined to at least one edge of each of the slots, wherein each of the flaps protrude in a substantially orthogonal fashion from the face plate and in a direction away from the top plate.

Abstract: A framing template tool may include a face plate; a top plate joined to the face plate at about an edge thereof, wherein the top plate is substantially orthogonal to the face plate; and alignment features. The alignment features may include slots formed in the face plate along its length; and one or more flaps joined to at least one edge of each of the slots, wherein each of the flaps protrude in a substantially orthogonal fashion from the face plate and in a direction away from the top plate.

Abstract: According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

Abstract: A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, sometimes denoted a bird's beak region. Wherein the transition region is implanted with germanium and boron, to prevent formation of leakage paths between active devices, or within an active device. The implanted area can be further limited to that area of the transition region that is adapted to be covered by a gate material, such as polysilicon.

Abstract: A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, sometimes denoted a bird's beak region. Wherein the transition region is doped with germanium and boron, to prevent formation of leakage paths between active devices, or within an active device. The doped area can be further limited to that area of the transition region that is adapted to be covered by a gate material, such as polysilicon.

Abstract: A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, sometimes denoted a bird's beak region. Wherein the transition region is implanted with germanium and boron, to prevent formation of leakage paths between active devices, or within an active device. The implanted area can be further limited to that area of the transition region that is adapted to be covered by a gate material, such as polysilicon.

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.

Abstract: A method of forming a recessed electrically-insulating field oxide region in a semiconductor substrate is disclosed.

Abstract: An H-transistor, fabricated in a silicon-on-insulator ("SOI") substrate, includes opposing source and drain terminals or regions flanking a centrally-located body node or well. Above the body node or well is formed the H-shaped gate terminal of the transistor. One or more shunt body contacts or ties bisect the source terminal and connect the source terminal of the transistor to the underlying body node. In this way, the body node or well is no longer electrically "floating", but, instead, is connected to the fixed ground potential of the source terminal of the transistor.

Abstract: The present invention teaches a low voltage coefficient MOS capacitor, and a method of making such a capacitor, having substantially uniform parasitic effects over an operating voltage range and a low voltage coefficient. The capacitor comprises a first conductive layer superjacent a silicon on insulator ("SOI") substrate. The first conductive layer comprises heavily doped silicon having a first conductivity type, while the substrate comprises a second conductivity type. Further, the capacitor comprises an isolation trench surrounding the first conductive layer filled with a dielectric material. Positioned superjacent the first conductive layer is a dielectric layer, thereby forming a dielectric shell on all sides of the first conductive layer except for its upper face. Moreover, a second conductive layer is positioned superjacent the dielectric layer to form a low voltage coefficient capacitor.

Abstract: A digital silicon-on-insulator (SOI) H-transistor layout is disclosed for gate arrays. In the preferred embodiment, the invention basically comprises at least two H-transistors; the ends of each H-transistor terminate in two distinct regions of field oxide; the two sides of the H-transistor abut a body contact region; and each body contact region abuts a strip of field oxide, which has an underlying trench. This pattern is repeated vertically and horizontally, generating a structure compatible for gate array architecture. In a gate array, all transistors in a column are of the same type, such as N type or P type. Within a row, however, the transistors types could alternate.

Abstract: An SOI circuit includes a set of buried body ties that provide ohmic contact to the otherwise floating transistor bodies disposed on an insulating layer and both provide a path for holes generated by impact ionization and also act as a potential shield between the substrate potential and the transistor sources. The same fabrication technique provides a buried interconnect layer between transistors that can be employed as a mask programmable local interconnect in an ASIC such as a gate array. The process provides for independent control of differential mesa thickness and buried body tie thickness, so that fully and partially depleted transistors can be fabricated simultaneously and placed on appropriate mesas without affecting the body ties.

Abstract: A radiation-hardened field oxide comprises a thin layer of high-quality thermal oxide, a thick layer of borophosphosilica glass and a diffusion barrier layer of undoped oxide, with the boron and phosphorous provising recombination sites for electron-hole pairs.