Abstract: In one embodiment, a computing system may determine a quantization range having a first quantization endpoint and a second quantization endpoint. While fixing the second quantization endpoint to an initial value determined based on the color range, one of a plurality of first candidate values for the first quantization endpoint is selected based on a plurality of corresponding first quantization errors. While fixing the first quantization endpoint to the selected first candidate value, one of a plurality of second candidate values for the second quantization endpoint is selected based on a plurality of corresponding second quantization errors. The computing system may define quantization levels corresponding to the bit depth using the quantization range defined by the first quantization endpoint and the second quantization endpoint, and then encode the one or more color components of the pixel region using the quantization levels.

Abstract: In one embodiment, a computing system may access color components of a pixel region in an image, and then determine a color variance for each of the color components. The computing system may further determine a desired bit allocation for each of the color components based on the color variance associated with that color component. The computing system may then determine a total bit allocation for the pixel region based on the desired bit allocations for the color components, as well as a number of unallocated bits available for allocation. The computing system may further determine a final bit allocation for each of the color components by allocating the total bit allocation to each of the color components according to the desired bit allocation for each of the color components. The computing system may then encode each of the color components using the associated final bit allocation.

Abstract: This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

Abstract: This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

Abstract: Disclosed herein includes a system, a method, and a device for compressing image data. The device includes one or more processors, coupled to memory, configured to identify a plurality of sub-blocks of a block of image data including a first sub-block and a second sub-block. The one or more processors are configured to identify a first data characteristic of data of the first sub-block and a second data characteristic of data of the second sub-block, determine a first compression technique based at least on the first data characteristic of the first sub-block, determine a second compression technique based at least on the second data characteristic of the second sub-block, and compress the first sub-block using the first compression technique and the second sub-block using the second compression technique.

Abstract: This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

Abstract: Disclosed herein a system, a method and a device for reducing a size and power consumption in encoder and decoder frame buffers using lossy compression. An encoder of a first device can provide a first video frame for encoding, to a prediction loop of the first device. In the prediction loop, lossy compression can be applied to the first video frame to generate a first compressed video frame. In the prediction loop, lossy decompression can be applied to the first compressed video frame. The encoder can provide, to a decoder of a second device to perform decoding, encoded video data corresponding to the first video frame and a configuration of the lossy compression.

Abstract: In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The second control unit may be configured to obtain, from the first control unit, a first memory address associated with a data writing process of the first processing unit, receive a read request from the second processing unit, the read request having an associated second memory address, and delay execution of the read request based on a comparison of the first memory address and the second memory address.

Abstract: In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.