Abstract: A system includes an isolated converter having a power transformer with a primary winding, a secondary winding, and an auxiliary winding. The system also includes: 1) a first switch coupled to the primary winding; 2) a switch controller coupled to the first switch; and 3) a bias power regulator circuit coupled to the auxiliary winding and the switch controller. The bias power regulator circuit includes a second switch. The bias power regulator circuit is configured to provide a bias supply output voltage to the switch controller based on a first set of modes that modulate a switching frequency of the second switch and based on a second mode in which the second switch stays off.

Abstract: A system includes an isolated converter having a power transformer with a primary winding, a secondary winding, and an auxiliary winding. The system also includes: 1) a first switch coupled to the primary winding; 2) a switch controller coupled to the first switch; and 3) a bias power regulator circuit coupled to the auxiliary winding and the switch controller. The bias power regulator circuit includes a second switch. The bias power regulator circuit is configured to provide a bias supply output voltage to the switch controller based on a first set of modes that modulate a switching frequency of the second switch and based on a second mode in which the second switch stays off.

Abstract: A system includes an isolated converter having a power transformer with a primary winding, a secondary winding, and an auxiliary winding. The system also includes: 1) a first switch coupled to the primary winding; 2) a switch controller coupled to the first switch; and 3) a bias power regulator circuit coupled to the auxiliary winding and the switch controller. The bias power regulator circuit includes a second switch. The bias power regulator circuit is configured to provide a bias supply output voltage to the switch controller based on a first set of modes that modulate a switching frequency of the second switch and based on a second mode in which the second switch stays off.

Abstract: In some examples, a circuit includes an input circuit, an output circuit, an auxiliary circuit, and a balancing circuit. The input circuit comprises a primary capacitor coupled to primary windings of a transformer. The output circuit comprises a secondary capacitor coupled to secondary windings of the transformer, wherein the secondary windings are coupled to the primary windings. The auxiliary circuit comprises auxiliary windings coupled to the primary windings. The balancing circuit is coupled to the output circuit, the auxiliary circuit, and the input circuit. The balancing circuit is configured to balance a voltage across the primary capacitor with a voltage across the secondary capacitor.

Abstract: An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the TD(L-H) optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the TD(H-L) optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the TDM optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Abstract: In some examples, a circuit includes an input circuit, an output circuit, an auxiliary circuit, and a balancing circuit. The input circuit comprises a primary capacitor coupled to primary windings of a transformer. The output circuit comprises a secondary capacitor coupled to secondary windings of the transformer, wherein the secondary windings are coupled to the primary windings. The auxiliary circuit comprises auxiliary windings coupled to the primary windings. The balancing circuit is coupled to the output circuit, the auxiliary circuit, and the input circuit. The balancing circuit is configured to balance a voltage across the primary capacitor with a voltage across the secondary capacitor.

Abstract: A power converter circuit includes a power stage comprising a transformer and a power switch. The power switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node having a switching voltage between the power switch and the primary winding. A switching controller includes a control transistor device to initiate an operational voltage associated with the control transistor device during a startup mode of the power converter circuit and to provide a control voltage based on an amplitude of the switching voltage during a normal operating mode. The switching controller generates the PWM signal in response to comparing the control voltage and a predetermined switching threshold voltage.

Abstract: A switch-mode power supply includes a transformer, a power transistor, pulse generation circuitry, and a dual ramp modulation (DRM) circuit. The power transistor is coupled to a primary coil of the transformer. The pulse generation circuitry is configured to generate a power transistor activation signal. The DRM circuit is coupled to the pulse generation circuitry. The DRM circuit is configured to generate a leading edge blank time signal that disables inactivation of the power transistor activation signal for a predetermined interval (a leading edge blank time) after a leading edge of the power transistor activation signal. The DRM circuit is also configured to generate a reset signal that inactivates the power transistor activation signal while the leading edge blank time signal is activated.

Abstract: Described examples include a semiconductor device having a resistor. The resistor includes a first terminal and a second terminal. The resistor also includes a first resistive element over an insulating layer over a substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor; and a parallel second resistive element over the insulating layer over the substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor. The resistor may also be coupled in series with another resistor.

Abstract: Described examples include a semiconductor device having a resistor. The resistor includes a first terminal and a second terminal. The resistor also includes a first resistive element over an insulating layer over a substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor; and a parallel second resistive element over the insulating layer over the substrate having a first end coupled to the first terminal of the resistor and a second end coupled to the second terminal of the resistor. The resistor may also be coupled in series with another resistor.

Abstract: A system includes an isolated converter having a power transformer with a primary winding, a secondary winding, and an auxiliary winding. The system also includes: 1) a first switch coupled to the primary winding; 2) a switch controller coupled to the first switch; and 3) a bias power regulator circuit coupled to the auxiliary winding and the switch controller. The bias power regulator circuit includes a second switch. The bias power regulator circuit is configured to provide a bias supply output voltage to the switch controller based on a first set of modes that modulate a switching frequency of the second switch and based on a second mode in which the second switch stays off.

Abstract: An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the TD(L?H) optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the TD(H?L) optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the TDM optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

Abstract: An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the TD(L-H) optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the TD(H-L) optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the TDM optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

Abstract: A switch-mode power supply includes a transformer, a power transistor, pulse generation circuitry, and a dual ramp modulation (DRM) circuit. The power transistor is coupled to a primary coil of the transformer. The pulse generation circuitry is configured to generate a power transistor activation signal. The DRM circuit is coupled to the pulse generation circuitry. The DRM circuit is configured to generate a leading edge blank time signal that disables inactivation of the power transistor activation signal for a predetermined interval (a leading edge blank time) after a leading edge of the power transistor activation signal. The DRM circuit is also configured to generate a reset signal that inactivates the power transistor activation signal while the leading edge blank time signal is activated.

Abstract: A power converter circuit includes a power stage comprising a transformer and a power switch. The power switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node having a switching voltage between the power switch and the primary winding. A switching controller includes a control transistor device to initiate an operational voltage associated with the control transistor device during a startup mode of the power converter circuit and to provide a control voltage based on an amplitude of the switching voltage during a normal operating mode. The switching controller generates the PWM signal in response to comparing the control voltage and a predetermined switching threshold voltage.

Abstract: A switch-mode power supply includes a transformer, a power transistor, pulse generation circuitry, and a dual ramp modulation (DRM) circuit. The power transistor is coupled to a primary coil of the transformer. The pulse generation circuitry is configured to generate a power transistor activation signal. The DRM circuit is coupled to the pulse generation circuitry. The DRM circuit is configured to generate a leading edge blank time signal that disables inactivation of the power transistor activation signal for a predetermined interval (a leading edge blank time) after a leading edge of the power transistor activation signal. The DRM circuit is also configured to generate a reset signal that inactivates the power transistor activation signal while the leading edge blank time signal is activated.

Abstract: An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the TD(L-H) optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the TD(H-L) optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the TDM optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

Abstract: Methods of operating switching power supplies are disclosed. A power supply has a transformer and a switch coupled to the primary side of the transformer for controlling the current flow through the primary side of the transformer. A method includes determining the output voltage of the power supply. A first minimum switching frequency is generated for driving the switch in response to the output voltage being greater than a nominal output voltage and less than a predetermined voltage. A second minimum switching frequency is generated for driving the switch in response to the output voltage being equal to or greater than the predetermined voltage, wherein the first minimum switching frequency is greater than the second minimum switching frequency.