Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Abstract: The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b?; 113b?). Formation of the fin-like channel region (113b?; 113b?) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1?-S4?); anisotropic etching of the active region (1) using the modified hard mask (S1?-S4?) forming widened STI trenches (G1?-G5?), the fin-like channel regions (113b?; 113b?) of the active region (1) remaining for each individual FinFET transistor.

Abstract: A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer.

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.

Abstract: A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

Abstract: An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

Abstract: A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating layer is formed on the first semiconductor layer. An electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned. The first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask. Furthermore, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer.

Abstract: A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.

Abstract: Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

Abstract: A memory cell having a storage capacitor and a vertical switching transistorm, which has a semiconducting nanostructure which has grown on at least part of the storage capacitor and includes a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod.

Abstract: Process for producing a multilayer arrangement having a metal layer, in which a metal layer is applied to a surface of a first wafer and at least one interlayer is applied to the metal layer. Furthermore, a second wafer is applied to the interlayer and then the first wafer is removed, so that the metal layer is uncovered.

Abstract: Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions.

Abstract: An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.

Abstract: Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer.

Abstract: Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located between a channel region essentially in and/or on a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, the channel region being arranged in each case at least partly laterally overlapping the floating gate and the read gate electrode.