Abstract: A surgical instrument, has an end effector that includes an ultrasonic blade, and a clamp arm that moves relative to the ultrasonic blade from an opened position toward an intermediate position and a closed position. The clamp arm is offset from the ultrasonic blade to define a predetermined gap in the intermediate position between the opened position and the closed position. A clamp arm actuator connects to the clamp arm and moves from an opened configuration to a closed configuration to direct the clamp arm from the opened position toward the intermediate position and the closed position. A spacer connects with the clamp arm to inhibit movement of the clamp arm from the intermediate position toward the closed position for maintaining the predetermined gap between the clamp arm and the ultrasonic blade.

Abstract: A conveyor belt module includes a laterally-extending protrusion to prevent misorientation of the module during assembly. In a proper orientation, the laterally-extending protrusion extends into a recess of an adjacent conveyor belt module, with clearance between the protrusion and the nadir of the recess. Reversal of the conveyor belt module prevents the conveyor belt module from fitting into a row of modules.

Abstract: A redundancy system for co-channel telecommunications comprising a first modem comprising a premapped symbol interface (PMSI) ROM configured to produce a constellation point number (CPN) value for each transmitted symbol using FEC codewords and a modulation format, an encoder to produce three CPN value signals, and a first symbol clock to generate a timing signal for the data signal. The system further comprises a second modem comprising a PMSI ROM decoder to decode the CPN values from the received CPN value signals, an interface bus to transmit the three CPN value signals of the encoder and the timing signal from the first online modem to the second offline modem, and a redundancy switch to switch the input channel of data to a FEC encoder of the second modem and the output channel of received codewords to a FEC decoder of the first modem in response to a redundancy switching signal.

Abstract: A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Abstract: A burst demodulator and method of obtaining a signal of interest from many signals of interest within a composite signal. Implementations may include receiving a composite signal, centering a replica of the interfering signal relative to the composite signal, reducing the composite signal to the bandwidth of a desired signal of interest, and canceling the remaining portion of the interfering signal.

Abstract: A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Abstract: An MPEG decoder (100-180) can use different formats (linear tiled etc) for image data memory (150) for reference pictures when decoding subsequent pictures. Each format brings advantages and disadvantages. The disclosure illustrates that it is possible for different video sequences to have characteristics which match one image buffer format well, but not another, for example where there is a lot of motion or only a little motion between images. Advantageously, the decoder employs a parameterised image buffer format and analysis of the incoming stream and/or measured decoding performance (190) so as to dynamically choose (90, 160, 170) the best image buffer format for the current part of a stream. Cache control features can also be controlled (198) to suit the particular data received.

Abstract: A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth.

Abstract: A portable computer device has data acceptance logic (24,40) that determines whether input data items have time and location information. If not, data items are stored together with time and location information taken from clock (30) and location determining circuitry (28), here a Global Positioning Service (GPS) system. A screen (6) is arranged to display data items in a time mode or a space mode. In the time mode, those data items with time information in a time interval are displayed on a time line. In a space mode, data items with time information in a display area are displayed, for example on a map of the display area. The display can be toggled between the time and space modes.

Abstract: A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Abstract: A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth.

Abstract: A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth.

Abstract: A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Abstract: An audiovisual system (10) has a first client (14) and a second client (16), each client (14, 16) being connected to a server (12). The first client (14) includes a television (18), while the second client (16) includes a small screen (20) and a stereo system (22). The server (12) stores data representing items for example video programmes or pieces of music, the data including one or more assets (28) describing each item. An asset (28) may be, for example, the name of a video programme or piece of music; metadata of an item (for example the artist, year of production, or album); a still picture (an album cover or single frame of a video); or a background image or advertisement for a user interface. A client (14, 16) presents assets (28) to the user in the form of a hierarchical user interface (30). The user up-dates the user interface (30) each time he adds an item to, or removes an item from, the server (12), or edits an asset (28) already stored on the server (12). FIG.

Abstract: An internal powerline network is provided with a routing device for routing a signal on only a part of the network. In this way the data capacity of the network is increased. The routing device is advantageously attached to the fuse box of the powerline network.

Abstract: A decoder has tuners for receiving data from different sources. Each tuner has an associated demultiplexer controlled to select a portion of a received signal corresponding to a selected channel or channels. The demultiplexer output to a remultiplexer configured to determine selected signal portions that have overlapping addresses, to reallocate addresses of the signal portions so there is no overlap, and to multiplex the signal portions for supply to a common interface slot.

Abstract: An image control system for controlling a menu on a display, comprises a menu arranged as a plurality of simultaneously displayed menu items in a loop and a selector (12) to select an item from the menu, the loop and the selector being moveable with respect to each other. A user input device (4) comprises a control device (6; 16) to generate a control signal to move the loop and the selector (12) relative to each other. The control device (6; 16) has a loop configuration, with movement around the loop of the control device causing corresponding relative movement between the selector (12) and the loop of the menu. Correlation between the loop configuration of the control device and the loop of menu items enables a user to intuitively navigate around a menu of items and select a desired one.

Abstract: An image control system for controlling a menu on a display, comprises a menu arranged as a plurality of simultaneously displayed menu items in a loop and a selector (12) to select an item from the menu, the loop and the selector being moveable with respect to each other. A user input device (4) comprises a control device (6; 16) to generate a control signal to move the loop and the selector (12) relative to each other. The control device (6; 16) has a loop configuration, with movement around the loop of the control device causing corresponding relative movement between the selector (12) and the loop of the menu. Correlation between the loop configuration of the control device and the loop of menu items enables a user to intuitively navigate around a menu of items and select a desired one.

Abstract: Apparatus for generating, from an environment, a description in the form of metadata such as an instruction set of a markup language comprises first sensor means for sensing a first aspect of the environment and converting means for converting the aspect into the metadata.

Abstract: A decoder expansion system (100,110) comprises a common interface card (100), a processor (120), a common interface slot (150) and storage means (130). The common interface card (100) is inserted into a common interface slot of a decoder (not shown) to route received data under control of the processor (120) to one or both of the common interface slot (150) and the storage means (130). The system is capable of manipulating the received data and outputting a signal to the decoder via the common interface card (100) to provide additional functionality to that provided by the decoder.