Abstract: Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

Abstract: Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

Abstract: A method and apparatus is provided for converting the frame rate of digital video data from one frame rate to another frame rate without introducing motion artifacts into the converted video data stream. A high frame rate video stream is converted into a lower frame rate video stream by selecting whole frames from the high frame rate video stream and outputting the selected frames as the lower frame rate video stream. To insure that only whole frames are selected from the high frame rate video stream, the frame rate of the high frame rate video stream is locked to the frame rate of the lower frame rate video stream. A frame cycle is defined to be an integer number of frames in the higher frame rate stream. The higher and lower frame rates are locked by repeatedly selecting and outputting as the lower frame rate video stream, over a time period that is substantially equal to one frame cycle, an integer number of frames from each frame cycle of the higher frame rate.

Abstract: A blackboard parallel processing system for carrying out a general processing task using a plurality of parallel processors. In one application of the blackboard processing system, a workstation (102), which is part of an an automated workstation manufacturing system (AWMS), includes a blackboard control unit (BCU) (106) on which four separate functions are implemented in separate identical modules. The BCU includes a database module (34) having access to a global database, which is available to each of the plurality of parallel processors, referred to as knowledge source processors (KSPs) (40). A trigger module (46) includes trigger patterns that are compared to the data developed from messages transmitted by the KSPs to initiate specific tasks according to a predefined sequence. A scheduler module (42) responds to the trigger signals, by transmitting a signal to initiate each task, either by a specified KSP or by the KSP that is the least loaded with previously assigned processing task.