Patents by Inventor Richard Maurice Barth
Richard Maurice Barth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120201089Abstract: An integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (DRAM). The first code indicates that data is to be written to the DRAM. The first code is registered by the DRAM on one or more edges of an external clock signal received by the DRAM. The strobe signal specifies one or more discrete points in time synchronous with the external clock signal at which the data is registered by the DRAM.Type: ApplicationFiled: April 19, 2012Publication date: August 9, 2012Applicant: RAMBUS INC.Inventors: Richard Maurice Barth, Frederick Abbott Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 7315929Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: April 30, 2007Date of Patent: January 1, 2008Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 7287109Abstract: Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is provided to the memory device during an odd phase of the clock signal.Type: GrantFiled: October 15, 2004Date of Patent: October 23, 2007Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 7213121Abstract: An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates a mode of operation of the integrated circuit memory device. The mode of operation is selected from at least one of a synchronous mode of operation and an asynchronous mode of operation. During the synchronous mode of operation, the circuit outputs the data in response to a transition of an external clock signal. During the asynchronous mode of operation, the circuit outputs the data after a period of time from when a transition of an external control signal is detected.Type: GrantFiled: May 6, 2005Date of Patent: May 1, 2007Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 7210015Abstract: An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.Type: GrantFiled: June 15, 2005Date of Patent: April 24, 2007Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 7085906Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: November 5, 2002Date of Patent: August 1, 2006Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 6931467Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: March 8, 2002Date of Patent: August 16, 2005Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 6810449Abstract: A system and method for performing data transfers within a computer system is provided The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: January 10, 2000Date of Patent: October 26, 2004Assignee: Rambus, Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 6591353Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: May 1, 2000Date of Patent: July 8, 2003Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 6542976Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: May 23, 2000Date of Patent: April 1, 2003Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Publication number: 20030061460Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: ApplicationFiled: November 5, 2002Publication date: March 27, 2003Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 6532522Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: November 21, 2000Date of Patent: March 11, 2003Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 6470405Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: May 29, 2001Date of Patent: October 22, 2002Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Publication number: 20020087790Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: ApplicationFiled: March 8, 2002Publication date: July 4, 2002Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 6405296Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: August 11, 2000Date of Patent: June 11, 2002Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Publication number: 20020004865Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: ApplicationFiled: May 29, 2001Publication date: January 10, 2002Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Publication number: 20010042182Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: ApplicationFiled: May 23, 2000Publication date: November 15, 2001Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 6209071Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.Type: GrantFiled: May 7, 1996Date of Patent: March 27, 2001Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Mark Alan Horowitz, Craig Edward Hampel, Frederick Abbot Ware
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Patent number: 6122688Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: November 26, 1997Date of Patent: September 19, 2000Assignee: Rambus Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin
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Patent number: 5966731Abstract: A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line.Type: GrantFiled: November 26, 1997Date of Patent: October 12, 1999Assignee: Rambus, Inc.Inventors: Richard Maurice Barth, Frederick Abbot Ware, John Bradly Dillon, Donald Charles Stark, Craig Edward Hampel, Matthew Murdy Griffin