Abstract: A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device reads data from the memory, shifting the data, and marks a good data unit as corrupted if the data unit constitutes a fractional portion of a corrupted EPU. The marking of the data unit is performed by inverting a parity bit of the data unit.

Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Abstract: A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.

Abstract: Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus environment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.

Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Abstract: Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a source domain. The source-enable signal may be controlled by a source-inhibit signal. The source-inhibit signal prevents the synchronous-pulse signal from producing the source enable signal and capture clock until data is available for transmission.

Abstract: Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus enviroment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.

Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Abstract: A method and apparatus for providing a configurable memory data width including a device supporting a first data width, a memory supporting a second data width, and a controller. The controller configures a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, and maps data from the device to the configured first sub-region of the memory. The controller implements a constant in an unused region of the memory, and calculates error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.

Abstract: Embodiments of the present invention provide for configurable memory bus width and memory reclamation. In particular, the memory controller is configured to use a width of memory that is less than that fully available such that back-to-back writes can occur, as opposed to read-modify-writes. Unused regions of memory (defined by the total available memory width subtracted by the managed memory width) are partially or fully reclaimed, thus increasing the effective memory size available to the user. The configuration methods accommodate multiple interface bus widths while maintaining bandwidth not previously possible.

Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. Te device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Abstract: A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.

Abstract: Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus enviroment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a data bus address. A decoder may provide bus segment information to the bridge independently of a bus transaction on the second data bus initiated by a source device. The bridge may comprise logic to forward the bus transaction on the first data bus to the target device based upon the bus segment information.

Abstract: Disclosed are a system and method of processing interrupt messages received on a data bus from a plurality of interrupt sources. The interrupt message receiver comprises logic to initiate an interrupt signal on one or more interrupt signal inputs to a controller in response to receipt of an interrupt message. The controller may then service the interrupt message in response to the interrupt signal.

Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Abstract: Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a source domain. The source-enable signal may be controlled by a source-inhibit signal. The source-inhibit signal prevents the synchronous-pulse signal from producing the source enable signal and capture clock until data is available for transmission.

Abstract: A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.