Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Abstract: Methods and apparatus are provided for programmable codeword encoding and decoding. Data blocks are represented as a number of codewords. Data is encoded into one or more full size codewords and at least one truncated codewords. Typically, data is encoded and decoded using one or more full size codewords and one truncated codeword. The truncated codewords are a two-dimensional array having a number of columns (or rows or both) less than the full size codeword. In this manner, the disclosed truncated codewords are adaptable to various system parameters that affect code rate.

Abstract: A circuit locks onto a frequency of data encoded on a medium, taking frequency variations in the physical travel of the medium into account. The circuit includes a disk locked clock (DLC) circuit having a synthesizer operating under digital control based on a feedback signal to produce a servo reference clock and a read reference clock that track frequency variations in the physical travel of the medium. A recovered clock signal is produced based on the servo reference clock and the read reference clock. A digital phase locked loop maintains a frequency lock of the recovered clock signal. An error measurement circuit is connected to the digital phase locked loop. The error measurement circuit produces the feedback signal for digitally controlling the digital logic circuit synthesizer to produce the servo reference clock and the read reference clock that track frequency variations in the physical travel of the medium.

Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.