Abstract: A synchronous multiple access interconnect system includes a bus and a plurality of master units each having a six state sequencer coupled to a plurality of serially connected AND gates, the bus and logic to provide signal settling time, generate handshake signals, receive handshake signals, transfer data, resolve contention for the bus between several requesting units and pass control of the bus in an orderly manner from one unit to another. Three signal lines of the bus pass control of the bus from one unit to another.

Abstract: Data is configured in 8 bit control characters and 8 bit data characters and stored in a terminal random access memory as a linked list structure. Control apparatus accesses the data stored in the terminal memory in 16 character blocks and identifies the accessed information as representing figures to be displayed, video enhancement features, or program execution path changes. Each two character link provides an address pointer to the next 16 character block of data and control information. The first character block of a line of displayable figures has links to the previous displayable line and the next line of characters to be displayed.The control apparatus combines internal hardware functions and the linked list encoding structure as implemented by program logic to provide display and control character identification, data access address modification, video display enhancement and selection of alternate character sets.