Patents by Inventor Richard Schooler

Richard Schooler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10397359
    Abstract: A solution is provided for selectively caching streaming media based on playback data associated with the streaming media. Each media stream is divided into a number of media chunks. Spatial locality and temporal locality of each media chunk is analyzed based on playback data of the media chunk and the corresponding media stream. Based on the spatial locality and temporal locality, a spatial score and temporal score are generated, respectively. Aggregation of the spatial score and temporal score produces a final score for the media chunk. The media chunks are ranked based on their final scores, where all or a number of media chunks are selected based on their rankings for being cached. The ranking of a cached media chunk decays over time, and the ranking of a cached media chunk is dynamically recalculated when another video chunk is to be cached.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 27, 2019
    Assignee: GOOGLE LLC
    Inventors: Richard Schooler, Pawel Jurczyk
  • Publication number: 20180191857
    Abstract: A solution is provided for selectively caching streaming media based on playback data associated with the streaming media. Each media stream is divided into a number of media chunks. Spatial locality and temporal locality of each media chunk is analyzed based on playback data of the media chunk and the corresponding media stream. Based on the spatial locality and temporal locality, a spatial score and temporal score are generated, respectively. Aggregation of the spatial score and temporal score produces a final score for the media chunk. The media chunks are ranked based on their final scores, where all or a number of media chunks are selected based on their rankings for being cached. The ranking of a cached media chunk decays over time, and the ranking of a cached media chunk is dynamically recalculated when another video chunk is to be cached.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Richard Schooler, Pawel Jurczyk
  • Patent number: 8949806
    Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: February 3, 2015
    Assignee: Tilera Corporation
    Inventors: Walter Lee, Robert A. Gottlieb, Vineet Soni, Anant Agarwal, Richard Schooler
  • Patent number: 8738860
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: May 27, 2014
    Assignee: Tilera Corporation
    Inventors: Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao, Christopher D. Metcalf, Bruce Edwards, Carl G. Ramey, Mark B. Rosenbluth, David M. Wentzlaff, Christopher J. Jackson, Ben Harrison, Kenneth M. Steele, John Amann, Shane Bell, Richard Conlin, Kevin Joyce, Christine Deignan, Liewei Bao, Matthew Mattina, Ian Rudolf Bratt, Richard Schooler
  • Patent number: 8458671
    Abstract: The present invention relates to a method, system, and computer program product for performing a computer program analysis. The computer program includes a plurality of instructions. The method performs a static analysis of the computer program to compute the states of a stack pointer (SP), a frame pointer (FP), and a link register (LR) at one or more instructions of the program. The static analysis is preferably performed at compile time. Further, the method computes the states of the SP, the FP, and the LR at the instructions as determined by a dynamic analysis, wherein the dynamic analysis is preferably modeled (performed) during the static analysis. Furthermore, the states determined by the static analysis and the dynamic analysis are compared. If a discrepancy is found between the two states, metadata (information operators) is inserted into the program.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: June 4, 2013
    Assignee: Tilera Corporation
    Inventors: Mathew Hostetter, Vineet Soni, Richard Schooler
  • Patent number: 8291400
    Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving subsets of instructions corresponding to different portions of a program, each subset assigned to one of the computation units; scheduling instructions in a given subset for execution on the assigned computation unit, including scheduling communication instructions that send to or receive from a different computation unit over the interconnection network; allocating registers in a given computation unit for storing values accessed by instructions in a subset assigned to the given computation unit; and scheduling instructions after allocating registers to account for spills of values stored in allocated register to memory, preserving the order of communication instructions scheduled before allocating registers.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: October 16, 2012
    Assignee: Tilera Corporation
    Inventors: Walter Lee, Robert A. Gottlieb, Vineet Soni, Anant Agarwal, Richard Schooler
  • Patent number: 8250555
    Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: August 21, 2012
    Assignee: Tilera Corporation
    Inventors: Walter Lee, Robert A. Gottlieb, Vineet Soni, Anant Agarwal, Richard Schooler
  • Patent number: 8250556
    Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving an initial partitioning of instructions into initial subsets corresponding to different portions of a program; forming a refined partitioning of the instructions into refined subsets each including one or more of the initial subsets, including determining whether to combine a first subset and a second subset to form a third subset according to a comparison of a communication cost between the first subset and second subset and a load cost of the third subset that is based at least in part on a number of instructions issued per cycle by a computation unit; and assigning each refined subset of instructions to one of the computation units for execution on the assigned computation unit.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: August 21, 2012
    Assignee: Tilera Corporation
    Inventors: Walter Lee, Robert A. Gottlieb, Vineet Soni, Anant Agarwal, Richard Schooler
  • Patent number: 8181168
    Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: May 15, 2012
    Assignee: Tilera Corporation
    Inventors: Walter Lee, Robert A. Gottlieb, Vineet Soni, Anant Agarwal, Richard Schooler
  • Patent number: 7827154
    Abstract: A method and mechanism for diagnosing application failures. An executable application is augmented with code which generates a list of components, as well as version information, utilized by the application. Also created is data which associates application components with applications which utilize those components. The list of components, version information, and association data are stored in a database and updated each time the application is run. In response to detecting a failure of the application, a database query is generated which returns a list of components utilized by the failed application. By comparing the date that application components changed to the date the application was last successfully run, a high priority list of components which changed since the last successful run may be generated. Diagnosis of the application failure may then begin with components in the high priority list.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: November 2, 2010
    Assignee: Symantec Operating Corporation
    Inventors: Michael P. Spertus, David A. Stuckmann, Richard Schooler, Christopher D. Metcalf
  • Patent number: 7823134
    Abstract: A computer method for issuing an early warning includes determining, using change and test coverage and control flow and data flow analyses of a program, locations in the program at which to insert early warning (EW) code to monitor for an event. The program is instrumented with EW code which monitors for the event, by inserting EW code at the determined locations. Upon detecting the event, EW code performs an early action warning, or issues an early action. Early warnings are issued when an EW-instrumented block is reached. Issuance of an early warning action can be conditional upon execution of the program in a particular environment, such as a production environment. Issuance of an EW can also be conditional upon executing an untested block of code that was recently modified.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: October 26, 2010
    Assignee: Symantec Operating Corporation
    Inventors: Anant Agarwal, Andrew E. Ayers, Richard Schooler
  • Patent number: 7739689
    Abstract: Methods and systems are provided for internal monitoring of applications. A distributed management framework may comprise a plurality of applications and application servers, wherein each of the applications is configured to make function calls to standard programming functions. The function calls to the standard programming functions are intercepted. The function calls are routed to alternative implementations of the standard programming functions, and the alternative implementations are used to collect availability metrics for the plurality of applications. Manager threads may be used for internal monitoring of application execution. Applications may be modified with additional instructions to monitor program execution and automatically generate output comprising an execution history.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 15, 2010
    Assignee: Symantec Operating Corporation
    Inventors: Michael P. Spertus, Christopher D. Metcalf, Richard Schooler, David A. Stuckmann
  • Patent number: 7543279
    Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: June 2, 2009
    Assignee: Symantec Operating Corporation
    Inventors: Andrew E. Ayers, Richard Schooler, Anant Agarwal
  • Publication number: 20040220774
    Abstract: A computer method for issuing an early warning includes determining, using change and test coverage and control flow and data flow analyses of a program, locations in the program at which to insert early warning (EW) code to monitor for an event. The program is instrumented with EW code which monitors for the event, by inserting EW code at the determined locations. Upon detecting the event, EW code performs an early action warning, or issues an early action. Early warnings are issued when an EW-instrumented block is reached. Issuance of an early warning action can be conditional upon execution of the program in a particular environment, such as a production environment. Issuance of an EW can also be conditional upon executing an untested block of code that was recently modified.
    Type: Application
    Filed: May 28, 2004
    Publication date: November 4, 2004
    Inventors: Anant Agarwal, Andrew E. Ayers, Richard Schooler
  • Publication number: 20040216092
    Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.
    Type: Application
    Filed: May 25, 2004
    Publication date: October 28, 2004
    Inventors: Andrew E. Ayers, Richard Schooler, Anant Agarwal
  • Patent number: 6804814
    Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: October 12, 2004
    Assignee: VERITAS Operating Corporation
    Inventors: Andrew E. Ayers, Richard Schooler, Anant Agarwal
  • Patent number: 6745383
    Abstract: A computer method for issuing an early warning includes determining, using change and test coverage and control flow and data flow analyses of a program, locations in the program at which to insert early warning (EW) code to monitor for an event. The program is instrumented with EW code which monitors for the event, by inserting EW code at the determined locations. Upon detecting the event, EW code performs an early action warning, or issues an early action. Early warnings are issued when an EW-instrumented block is reached. Issuance of an early warning action can be conditional upon execution of the program in a particular environment, such as a production environment. Issuance of an EW can also be conditional upon executing an untested block of code that was recently modified.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: June 1, 2004
    Assignee: Veritas Operating Corporation
    Inventors: Anant Agarwal, Andrew E. Ayers, Richard Schooler
  • Patent number: 6353924
    Abstract: A method of back-tracing execution of a computer program, where the computer program comprises a plurality of blocks, comprises instrumenting an original version of the program by adding instrumentation code to some or all of the blocks to form an instrumented program. Instrumentation can be added at the binary or source level, or at link time. The instrumentation code records execution sequence information upon execution of the corresponding instrumented block to create a trace record of the executed program. The execution sequence information for each block comprises a block identifier which identifies the corresponding block. A detailed back-trace is generated, after the program has executed, by replacing each recorded block identifier with program counters associated with each instruction in the corresponding block. The application may comprise several programs or subprograms, in which case separate regions of memory can be maintained.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: March 5, 2002
    Assignee: Incert Software Corporation
    Inventors: Andrew E. Ayers, Anant Agarwal, Richard Schooler
  • Patent number: 6308321
    Abstract: A method of generating a program control flow definition from the program code determines entry points in the program. The code is followed, or scanned, from an entry point to a branch or jump instruction, or control flow instruction. A code block is then defined as the code from the entry point up to and including the control flow instruction. From the control flow instruction, additional entry points are identified. This is repeated for each entry point having a known value, resulting in a partial control flow definition. For entry points having unknown values, a constant propagation analysis is performed on the partial control flow definition to convert unknown entry point values to known values. Finally, the entry points determined by the constant propagation analysis are used as starting points in the scanning step to define additional entry points.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: October 23, 2001
    Assignee: Incert Software Corporation
    Inventor: Richard Schooler
  • Patent number: 6038398
    Abstract: A compiler optimizing procedure improves a sequence of memory addressing actions of a program, wherein the program includes a plurality of do loops. The procedure includes the steps of: performing an interchange of do loops, within a set of nested loops, to move at least one loop of the set to a position of an outer loop, wherein the one loop manifests a condition which prevents application of a distribution action thereto; attempting a distribution of next outermost loops so as to isolate a code segment in the program from remaining interior loops in the set of nested loops; and if the distribution is performed, determining for each remaining interior loop if an interchange with another interior loop will improve an efficiency of execution of the program and if yes, performing the loop interchange.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: March 14, 2000
    Assignee: Hewlett-Packard Co.
    Inventor: Richard Schooler