Abstract: A distributed switch buffer and method for switch buffer enlargement use standard switch chips as modules that are cascaded in multiples to provide arbitrarily large switch buffers for any number of inputs and outputs. Any type of packet switch chip may be used in any combination. A packet that enters the first switch chip in the cascade automatically gets transferred to other switch chips as part of an integrated buffering scheme. Every input of the switch is connected to all of the switch chips in the first stage of the distributed buffer. The queue of each output of the switch is then expanded by adding more stages of switch chips. All outputs of each switch chip go to the inputs of the same switch chip in the next stage of the distributed buffer so that all of the buffer space of all the cascaded switch chips is available to each input port. The queue may be expanded indefinitely by cascading more chips.

Abstract: Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The ECL input is applied to the gate of the N-type transistor of the first inverter circuit. A threshold control circuit includes a CMOS inverter circuit with the gate of the N-type transistor connected to a reference voltage and the gate of the P-type transistor connected to its drain is connected to the gate of the P-type transistor of the first inverter circuit. The threshold control circuit adjusts the threshold voltage of the first inverter circuit so as to compensate for changes in current flow through the N-type or P-type transistors, thereby permitting operation over extreme variations in circuit parameters under situations of poor operating tolerances and wide temperature variations.

Abstract: Electrical circuitry providing a compatible interface between ECL logic level of -1.6 and -0.8 volts and CMOS logic levels of 0 and +5 volts. Voltage sources of -3.7 and +1.3 volts are provided for supplying operating voltages to the CMOS circuitry in order to set the threshold voltage CMOS inverters at -1.2 volts, the threshold voltage of ECL logic circuits.