Abstract: A laser-based coating removal method debonds a film from a substrate rather than ablating the film. A laser light is transmitted through a transparent film to an underlying bonding layer for bonding the film to one or more additional films and/or a substrate. The laser light is absorbed at the bonding layer and the transparent film is released. In some embodiments, after the transparent film is released it is able to be physically removed.

Abstract: A laser-based coating removal method debonds a film from a substrate rather than ablating the film. A laser light is transmitted through a transparent film to an underlying bonding layer for bonding the film to one or more additional films and/or a substrate. The laser light is absorbed at the bonding layer and the transparent film is released. In some embodiments, after the transparent film is released it is able to be physically removed.

Abstract: A laser-based coating removal method debonds a film from a substrate rather than ablating the film. A laser light is transmitted through a transparent film to an underlying bonding layer for bonding the film to one or more additional films and/or a substrate. The laser light is absorbed at the bonding layer and the transparent film is released. In some embodiments, after the transparent film is released it is able to be physically removed.

Abstract: A non-volatile memory element is operated, in part, in two phases. During the first phase, a voltage is applied to a first node coupled to the nonvolatile memory element to generate an initial voltage. During the second phase, a voltage is coupled through at least one capacitor to charge pump the initial voltage to a level sufficient for programming or erasing the non-volatile memory element.

Abstract: Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state.

Abstract: Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state.

Abstract: The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.

Abstract: The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array.

Abstract: Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog recording and playback which provides increased resolution in the stored signal and increased accuracy and stability of the storage and readout capabilities of the device. The storage cell is configured wherein the electrically alterable MOS storage device is connected in a source follower configuration, which provides a one to one relationship between the variation in the floating gate storage charge and the variation in the output voltage, and for high load resistance, relative insensitivity to load characteristics. The write process and circuitry provides a multi iterative programming technique wherein a series of coarse pulses program a cell to the approximate desired value, with a series of fine pulses referenced to the last coarse pulse being used for programming the respective cell in fine increments to a desired final programming level. Still finer levels of programming can be used.

Abstract: The present invention is a high density integrated circuit analog signal recording and playback system. The recording and playback system is based upon an array storing analog signals. The array has rows and columns of non-volatile memory cells to store the signal information. Analog column read/write circuitry is used to both store the analog information and retrieve it on a real time basis, using interleaving of analog information on a plurality of sample/hold circuits prior to storage in the array to increase throughput.

Abstract: The present invention is a high density integrated circuit analog signal recording and playback system. The recording and playback system is based upon an array storing analog signals. The array has rows and columns of non-volatile memory cells to store the signal information. Analog column read/write circuitry is used to both store the analog information and retrieve it on a real time basis, using interleaving of analog information on a plurality of sample/hold circuits prior to storage in the array to increase throughput.

Abstract: Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

Abstract: Integrated high voltage clamping methods and devices which provide a controllable "soft" clamping action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.

Abstract: Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

Abstract: Integrated circuit high voltage ramp rate control methods and devices which provide a controllable ramp rate action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.

Abstract: A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with three layers of polysilicon and a substrate coupling electrode is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration. The substrate electrode is used to establish bias voltages in the cell.

Abstract: An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Abstract: Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

Abstract: A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with four layers of polysilicon is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration.