Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: A high pass filter adapted for use in a signal processing device comprising a sampler adapted to sample a signal and transmit the samples to the high pass filter, the high pass filter comprising a differentiator and an integrator; a counter which, in use, counts the number of samples received by the high pass filter from the sampler; and a control device which receives a first signal from the counter when the high pass filter has received a first sample from the sampler and receives a second signal from the counter when the high pass filter has received a second or subsequent sample from the sampler; whereupon receipt of the first signal, the control device causes the integrator output signal to substantially equal zero and whereupon receipt of the second signal, the control device causes the integrator output to be a function of an input signal from the differentiator.