Abstract: A method for producing hydrogen and carbon from hydrocarbons in a reaction chamber is provided. The method includes introducing a hydrocarbon into a chamber such that the hydrocarbon rotates in a first direction. The method includes generating a direct current (DC)-based plasma from a portion of the hydrocarbon, wherein the hydrocarbon is heated to a temperature greater than 1,000° C. at least in part by the DC-based plasma. The method includes rotating the DC-based plasma in a second direction that is different from the first direction. The method includes converting the hydrocarbon into elemental constituents of the hydrocarbon comprising carbon solid and hydrogen gas. The method includes separating the carbon solid from the hydrogen gas to provide a solid part and a gas part.

Abstract: A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational profile formed according to a subset of steps within a sequence of steps of the integrated circuit production methodology that culminates in a production integrated circuit intended for use by a consumer. According to an embodiment, the integrated circuit elevational profile may be fabricated according to a majority of the sequence of steps. Alternatively, the integrated circuit elevational profile may be fabricated according to a minority of the sequence of steps. The test structure may be fabricated upon die sites designated to receive the test structure. Alternatively, the test structure may be fabricated upon die sites otherwise intended for operable integrated circuits.

Abstract: A test structure for characterizing ion implantation procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a first dielectric layer, a patterned polysilicon layer, and a second dielectric layer arranged in order upon a substrate. Ion implantation of the second dielectric layer may be performed according to a procedure used in the fabrication of integrated circuits. The ion-implanted regions of the second dielectric layer may be preferentially removed relative to non-ion-implanted regions of the second dielectric layer. A metal silicide may then be selectively formed upon portions of the patterned polysilicon not covered by non-removed regions of the second dielectric layer. Electrical testing and/or optical inspection may be used to identify defects introduced into the test structure during ion implantation.

Abstract: A test structure which includes a first conductive feature layer and a second conductive feature layer is described. The first conductive feature layer includes a first conductive line. The second conductive feature layer includes a second conductive line. A daisy chain conductive feature is also included in the test structure. The daisy chain conductive feature includes portions on the first and second conductive feature layers which are interconnected to each other by vias.

Abstract: A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines when the test structure is inspected. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure.

Abstract: A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a complete or substantially complete production integrated circuit topography. According to an alternative embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a partially complete production topography. The test structure and method may be used to characterize the underlying elevational profile and to identify both systematic and random defects either as part of routine monitoring or in response to the observance of defective chips using other monitoring.

Abstract: A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. A number of intentional partial defects may be formed at predetermined locations along the test structure. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure.

Abstract: A test structure for characterizing etching procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a contrast layer, a simulated substrate, and a pattern layer arranged in order upon a substrate. The simulated substrate includes portions mimicking a semiconductor substrate and portions mimicking isolation regions. Etching of the pattern layer may be performed according to a procedure used in the fabrication of integrated circuits. The contrast layer may be selectively etched relative to the substrate, the simulated substrate, and the pattern layer. Exposure of the etched test structure to a wet etchant selective for the contrast layer may be used to identify defects resulting from over-etching or other errors in the integrated circuit fabrication procedure being tested.

Abstract: According to an example embodiment of the present invention, a semiconductor device having conductive structure is analyzed using acoustic energy. Acoustic energy is generated in the device, and a resulting acoustic wave is detected. Using the detected wave, an index of refraction of a portion of the conductive structure is determined as a function of the wave. The calculated index of refraction is used and at least one defect in the conductive structure is detected. Using this method, defects can be detected during or after the manufacture of semiconductor devices in a cost effective, reliable manner. This method is particularly useful for defects that are not detectable using typical optical scanning methods due to opaque material in semiconductor devices.

Abstract: A method is presented for determining a predicted yield value for a silicon wafer subjected to a wafer fabrication process. The wafer fabrication process forms multiple integrated circuits (i.e., chips) upon a surface of the wafer. A unit cell region is chosen on the surface of the wafer and within the boundaries of a single chip. Two or more masking steps which form features within the selected unit cell region are chosen as critical masking steps. Portions of the unit cell region within which a given critical masking step forms features with minimum dimensions or spacings are identified as critical regions. A fraction of the unit cell region enveloped by critical regions is used to compute a critical chip area A' for the critical masking step. An electrical fault density D' is computed for each critical masking step as a product of an expected total defect density D.sub.t and a fraction of defects expected to result in catastrophic failures f.sub.c.