Abstract: A floating-point adder circuit is described. The circuit comprises an input multiplexer coupled to receive a first input value and a second input value; an adder-subtractor circuit selectively coupled to receive one of the first input value and the second input value at each of a first input and a second input, wherein the value coupled to the second input is added to or subtracted from the value coupled to the first input; a right shift circuit for aligning the smaller of the first input value and the second input value which is coupled to the second input of the adder-subtractor circuit; and an additional shift circuit (e.g., a left shift/right shift circuit of a combined near path and far path) coupled to the output of the adder-subtractor circuit. A method of implementing a floating-point adder is also disclosed.

Abstract: Architecture of a digital signal processing engine and method for digital signal processing therewith are described. Instruction memory stores an instruction which has at least one opcode which is selected from a group consisting of a control opcode, a digital signal processing (DSP) opcode, and a memory opcode. A digital signal processing engine includes a controller for receiving the control opcode, a DSP core for receiving the DSP opcode, and a memory interface for receiving the memory opcode. The controller, the digital signal processing core, and the memory interface are separate pipelines at least two of which have different numbers of stages. The controller may include an arithmetic logic unit, a base address regfile, and a branch/decode circuit.