Patents by Inventor Richard Wendell Foote, Jr.

Richard Wendell Foote, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9716167
    Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: July 25, 2017
    Assignee: National Semiconductor Corporation
    Inventors: Yaojian Leng, Richard Wendell Foote, Jr., Steven J. Adler
  • Patent number: 8878295
    Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 4, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Alexei Sadovnikov, William French, Erika Mazotti, Richard Wendell Foote, Jr., Punit Bhola, Vladislav Vashchenko
  • Patent number: 8524548
    Abstract: A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: September 3, 2013
    Assignee: National Semiconductor Corporation
    Inventors: William French, Vladislav Vashchenko, Richard Wendell Foote, Jr., Alexei Sadovnikov, Punit Bhola, Peter J. Hopper
  • Publication number: 20120273881
    Abstract: A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
    Type: Application
    Filed: April 26, 2011
    Publication date: November 1, 2012
    Inventors: William French, Vladislav Vashchenko, Richard Wendell Foote, JR., Alexei Sadovnikov, Punit Bhola, Peter J. Hopper
  • Publication number: 20120261753
    Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: Peter J. Hopper, Alexei Sadovnikov, William French, Erika Mazotti, Richard Wendell Foote, JR., Punit Bhola, Vladislav Vashchenko
  • Publication number: 20120211826
    Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.
    Type: Application
    Filed: February 22, 2011
    Publication date: August 23, 2012
    Inventors: Yaojian Leng, Richard Wendell Foote, JR., Steven J. Adler
  • Patent number: 7633373
    Abstract: A thin film resistor is formed to have very accurately defined dimensions which, in turn, allow the resistive value of the resistor to be very accurately defined. The resistor is formed on spaced-apart conductive pads which, in turn, are electrically connected to conductive plugs that are spaced apart from the resistor.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: December 15, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Joseph A. De Santis, Richard Wendell Foote, Jr.
  • Patent number: 7390722
    Abstract: An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device layer on the wafer, whereby both patterns can be printed in a single photolithographic operation. The same oxidation process used to produce an isolating oxide between active device regions of the active device layer can also be used to produce the positional reference structure.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: June 24, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Richard Wendell Foote, Jr.
  • Patent number: 7230517
    Abstract: A system and method is disclosed for using plasma to adjust the resistance of a thin film resistor. In one advantageous embodiment of the invention, the resistance of a thin film resistor is increased to cause the thin film resistor to have a desired higher value of resistance. The thin film resistor is formed having an initial value of resistance that is less than the desired value of resistance. Then the thin film resistor is placed in an oxidizing atmosphere. A surface of the thin film resistor is then oxidized to increase the initial value of resistance to the desired value of resistance. The amount of the increase in resistance may be selected by selecting the temperature of the oxidizing atmosphere.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: June 12, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Richard Wendell Foote, Jr., Tom Bold, Rodney Hill, Abhay Ramrao Deshmukh