Patents by Inventor Richard Y. Chang
Richard Y. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082202Abstract: Methods and compositions containing a phorbol ester or derivative of a phorbol ester are provided for prevention and treatment of sudden acute respiratory syndrome (SARS) coronavirus infection, including SARS-CoV-2 infection and related COVID-19 disease. Also provided are methods and compositions for preventing and treating acute inflammatory conditions and related pathogenic injuries, including Acute Respiratory Distress Syndrome (ARDS) and cytokine storm syndrome (CSS) seen in severe SARS-CoV-2/COVID-19 cases.Type: ApplicationFiled: November 10, 2023Publication date: March 14, 2024Inventors: Richard L. CHANG, Ben Y. CHANG
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Patent number: 9490812Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: January 28, 2014Date of Patent: November 8, 2016Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8680913Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: May 13, 2013Date of Patent: March 25, 2014Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8441314Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: July 26, 2012Date of Patent: May 14, 2013Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8253484Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: October 28, 2011Date of Patent: August 28, 2012Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 8072260Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: November 22, 2010Date of Patent: December 6, 2011Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 7859329Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: November 25, 2009Date of Patent: December 28, 2010Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang
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Patent number: 7646237Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: July 30, 2007Date of Patent: January 12, 2010Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y Chang
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Patent number: 7286007Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: November 17, 2005Date of Patent: October 23, 2007Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y Chang
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Patent number: 7236007Abstract: Methods and system for achieving improved copyright protection for programmable logic devices are disclosed. One preferred embodiment comprises a programmable logic device comprising a programmable element programmed by a mutated programming pattern, said mutated programming pattern causing the PLD to generate a mutated output; and a circuit element that translates the mutated output into a normal output.Type: GrantFiled: September 24, 2004Date of Patent: June 26, 2007Assignee: Altera CorporationInventor: Richard Y. Chang
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Patent number: 7119574Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE?Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.Type: GrantFiled: August 8, 2003Date of Patent: October 10, 2006Assignee: Altera CorporationInventors: Andy L Lee, Wanli Chang, Cameron McClintock, John E Turner, Brian D Johnson, Chiao Kai Hwang, Richard Y Chang, Richard G Cliff
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Patent number: 7075365Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.Type: GrantFiled: April 22, 2004Date of Patent: July 11, 2006Assignee: Altera CorporationInventors: Gregory Starr, Kang Wei Lai, Richard Y. Chang