Abstract: A current sense loop includes an attenuator circuit, which has an embedded input chopper circuit, and an amplifier circuit, which has an output chopper circuit. The embedded input chopper has a first chopper input that is coupled to a first attenuator input, a first chopper output that is coupled to a first attenuator output, a second chopper input that is coupled to a second attenuator input, and a second chopper output that is coupled to a second attenuator output. An amplifier has a first input coupled to the first attenuator output and a second input coupled to the second attenuator output. An NFET has a gate coupled to the amplifier output, a source coupled to a ground plane, and a drain coupled to the second attenuator input.

Abstract: A current sense loop includes an attenuator circuit, which has an embedded input chopper circuit, and an amplifier circuit, which has an output chopper circuit. The embedded input chopper has a first chopper input that is coupled to a first attenuator input, a first chopper output that is coupled to a first attenuator output, a second chopper input that is coupled to a second attenuator input, and a second chopper output that is coupled to a second attenuator output. An amplifier has a first input coupled to the first attenuator output and a second input coupled to the second attenuator output. An NFET has a gate coupled to the amplifier output, a source coupled to a ground plane, and a drain coupled to the second attenuator input.

Abstract: A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected.

Abstract: A load switch circuit implemented on an IC chip includes a first node for coupling to an input voltage, a second node for coupling to an external load, first and second capacitor nodes for coupling to first and second terminals of an external capacitor, and a first PFET coupled between the first node and the second node to control an output voltage to the external load. The load switch circuit also includes a driver circuit having a first NFET that has a drain coupled to the first node and a source coupled to a gate of the first PFET. A slew-rate-control circuit is coupled to a gate of the first NFET and includes the first capacitor node, which is coupled to the gate of the first NFET, and the second capacitor node, which is coupled to the second node.

Abstract: An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.

Abstract: A load switch circuit implemented on an IC chip includes a first node for coupling to an input voltage, a second node for coupling to an external load, first and second capacitor nodes for coupling to first and second terminals of an external capacitor, and a first PFET coupled between the first node and the second node to control an output voltage to the external load. The load switch circuit also includes a driver circuit having a first NFET that has a drain coupled to the first node and a source coupled to a gate of the first PFET. A slew-rate-control circuit is coupled to a gate of the first NFET and includes the first capacitor node, which is coupled to the gate of the first NFET, and the second capacitor node, which is coupled to the second node.

Abstract: A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected.

Abstract: An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the samples to modify drive parameters. Use of multiple sample periods enables independent measurement and adjustment of different portions of the transducer driving waveform to ensure mirror symmetry.

Abstract: Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

Abstract: Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

Abstract: A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator comprises an input stage with a negative voltage reference node, a first differential input coupled to a first differential pair transistor and operative to receive a first input signal, and a second differential input coupled to a second differential pair transistor and operative to receive a second input signal. The first input signal and the second input signal form a differential input signal. The differential comparator further comprises a common mode sensing circuit interconnected between the first differential input, the second differential input, and the negative voltage reference node. The common mode sensing circuit is operative to sense a common mode voltage of the differential input signal and set a voltage potential at the negative voltage reference node substantially equal to the sensed common mode voltage.

Abstract: Systems are provided for reducing electromagnetic emissions from a controller area network transceiver. A driver circuit is operative to transmit communications across an associated bus. A static driver replica circuit approximates a common-mode voltage associated with a dominant state associated with the bus. A receiver attenuator bias circuit forces a common-mode voltage associated with the driver circuit to be equal to the approximated dominant state common-mode voltage during a recessive state associated with the bus.

Abstract: A system and method is provided for translating a wide common mode voltage range into a narrow common mode voltage range. The system and method extend the common mode voltage range of functional devices beyond the supply rails of the functional device, while keeping the differential signal loss to a minimum. The system and method translate a common mode input signal from a wide common mode voltage range into a narrow common mode voltage range utilizing a feedback technique.

Abstract: A system and method is provided for translating a wide common mode voltage range into a narrow common mode voltage range. The system and method extend the common mode voltage range of functional devices beyond the supply rails of the functional device, while keeping the differential signal loss to a minimum. The system and method translate a common mode input signal from a wide common mode voltage range into a narrow common mode voltage range utilizing a feedback technique.