Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n?1 and (p+n+m)=N where m?0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Abstract: Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.

Abstract: A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.

Abstract: An electronic circuit and a method of making the same includes a multiplier circuit configured to perform a multiplication of a first input signal with a second input signal. The first input signal is a binary input signal that includes a sequence of input bits. The electronic circuit further includes an oscillator circuit configured to receive a result signal of the multiplication from the multiplier and to provide output pulses having an output frequency which is dependent on the result signal of the multiplication and a digital counter circuit configured to count the output pulses. The digital counter circuit is configured to provide a plurality of counter bits and to select one of the plurality of counter bits for incrementation in dependence on a significance of the corresponding input bit of the sequence of input bits.

Abstract: A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

Abstract: Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.

Abstract: A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

Abstract: The present disclosure relates to a method for implementing processing elements in a chip card such that the processing elements can communicate data between each other in order to perform a computation task, wherein the data communication requires each processing element to have a respective number of connections to other processing elements. The method comprises: providing a complete graph with an even number of nodes that is higher than the maximum of the numbers of connections by one or two. If the number of processing elements is higher that the number of nodes of the graph, the graph may be duplicated and the duplicated graphs may be combined into a combined graph. A methodology for placing and connecting the processing elements may be determined in accordance with the structure of nodes of a resulting graph, the resulting graph being the complete graph or the combined graph.

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n?1 and (p+n+m)=N where m?0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Abstract: The present disclosure relates to a method for implementing processing elements in a chip card such that the processing elements can communicate data between each other in order to perform a computation task, wherein the data communication requires each processing element to have a respective number of connections to other processing elements. The method comprises: providing a complete graph with an even number of nodes that is higher than the maximum of the numbers of connections by one or two. If the number of processing elements is higher that the number of nodes of the graph, the graph may be duplicated and the duplicated graphs may be combined into a combined graph. A methodology for placing and connecting the processing elements may be determined in accordance with the structure of nodes of a resulting graph, the resulting graph being the complete graph or the combined graph.

Abstract: A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

Abstract: A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.

Abstract: A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.