Patents by Inventor Riichi Sasamori

Riichi Sasamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11699801
    Abstract: A cell for water electrolysis/fuel cell power generation which includes a flow path configured to supply or discharge water in a first direction substantially perpendicular to a stacking direction of the cell; an oxygen-containing gas flow path configured to discharge or supply an oxygen-containing gas in a second direction substantially perpendicular to the stacking direction of the cell; and a hydrogen-containing gas flow path configured to discharge or supply the hydrogen-containing gas in a third direction substantially perpendicular to the stacking direction of the cell. Each of the oxygen-side electrode layer and the hydrogen-side electrode layer is an electrode layer having water repellency.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 11, 2023
    Inventors: Yoshitsugu Sone, Hiroshige Matsumoto, Yuki Terayama, Takamasa Haji, Riichi Sasamori, Motohiko Sato
  • Publication number: 20190252708
    Abstract: A cell for water electrolysis/fuel cell power generation which includes a flow path configured to supply or discharge water in a first direction substantially perpendicular to a stacking direction of the cell; an oxygen-containing gas flow path configured to discharge or supply an oxygen-containing gas in a second direction substantially perpendicular to the stacking direction of the cell; and a hydrogen-containing gas flow path configured to discharge or supply the hydrogen-containing gas in a third direction substantially perpendicular to the stacking direction of the cell. Each of the oxygen-side electrode layer and the hydrogen-side electrode layer is an electrode layer having water repellency.
    Type: Application
    Filed: November 1, 2017
    Publication date: August 15, 2019
    Inventors: Yoshitsugu SONE, Hiroshige MATSUMOTO, Yuki TERAYAMA, Takamasa HAJI, Riichi SASAMORI, Motohiko SATO
  • Patent number: 9224903
    Abstract: A method for manufacturing a photoelectric converter, comprising: forming a first buffer layer comprising a metal sulfide on a light-absorbing layer comprising a Group I-III-VI compound or a Group I-II-IV-VI compound; and contacting a surface of the first buffer layer with a first solution comprising an alkali metal compound.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 29, 2015
    Assignee: KYOCERA Corporation
    Inventors: Takeshi Suzuki, Riichi Sasamori, Junji Aranami, Hirofumi Senta
  • Publication number: 20150118789
    Abstract: A method for manufacturing a photoelectric converter (11), comprising: a first step of forming a first buffer layer (4) comprising a metal sulfide on a light-absorbing layer (3) comprising a Group I-III-VI compound or a Group I-II-IV-VI compound; and a second step of contacting a surface of the first buffer layer (4) with a first solution comprising an alkali metal compound.
    Type: Application
    Filed: March 11, 2013
    Publication date: April 30, 2015
    Inventors: Takeshi Suzuki, Riichi Sasamori, Junji Aranami, Hirofumi Senta
  • Publication number: 20120319244
    Abstract: A method for manufacturing a semiconductor layer according to an embodiment of the present invention comprises preparing a first compound, preparing a second compound, making a semiconductor layer forming solution, and forming a semiconductor layer including a group compound by using this semiconductor layer forming solution. The first compound contains a first chalcogen-element-containing organic compound, a first Lewis base, a I-B group element, and a first III-B group element. The second compound contains an organic ligand and a second III-B group element. The semiconductor layer forming solution contains the first compound, the second compound, and an organic solvent.
    Type: Application
    Filed: January 25, 2011
    Publication date: December 20, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Seiji Oguri, Keizo Takeda, Koichiro Yamada, Kotaro Tanigawa, Isamu Tanaka, Riichi Sasamori, Hiromitsu Ogawa
  • Patent number: 8227733
    Abstract: A multi-layer photoelectric conversion device and technology is disclosed. A first photoelectric converter is separated from a second photoelectric converter by an insulative layer. The photoelectric converters may be of a variety of types, and the insulative layer provides protection to reduce pinhole faults in the multi-layer photoelectric conversion device.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: July 24, 2012
    Assignee: KYOCERA Corporation
    Inventors: Hisashi Higuchi, Junji Aranami, Hisashi Sakai, Riichi Sasamori, Seigo Ito
  • Publication number: 20100243863
    Abstract: A multi-layer photoelectric conversion device and technology is disclosed. A first photoelectric converter is separated from a second photoelectric converter by an insulative layer. The photoelectric converters may be of a variety of types, and the insulative layer provides protection to reduce pinhole faults in the multi-layer photoelectric conversion device.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Applicant: Kyocera Corporation
    Inventors: Hisashi Higuchi, Junji Aranami, Hisashi Sakai, Riichi Sasamori, Seigo Ito
  • Patent number: 6207259
    Abstract: A wiring board comprising an insulating substrate containing at least an organic resin, a plurality of electrically conducting wiring layers formed on the surface and/or inside of said insulting substrate, and via-hole conductors formed in said insulating substrate in order to electrically connect the plurality of electrically conducting wiring layers, wherein said via-hole conductors contain an organic binder as well as a Cu—Sn intermetallic compound as an electrically conducting component. The via-hole conductors formed in the wiring board exhibit a high electric conductivity and a large heat resistance, making it possible to very highly reliably connect the electrically conducting wiring layers together.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: March 27, 2001
    Assignee: Kyocera Corporation
    Inventors: Yuji Iino, Riichi Sasamori, Katsura Hayashi, Masaaki Hori, Hidenori Shikada, Masaaki Harazono
  • Patent number: 6143116
    Abstract: A multilayer wiring board formed by laminating a plurality of circuit board units each including an insulating board containing at least a thermosetting resin, and a wiring circuit layer formed on the surface of said insulating board, wherein said insulating board is provided with via hole conducting passages so as to electrically connect the wiring circuit layers of the neighboring circuit board units, said via hole conducting passages are formed by filling via holes formed in the insulating board with a conducting paste, and said wiring circuit layer is buried in the surface of the insulating board in a manner that said insulating board possesses a flat surface. The multilayer wiring board has a satisfactory flatness required for mounting flip chips. Besides, the insulating board and the via hole conducting passages are not infiltrated by chemicals such as etching solution or plating solution.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: November 7, 2000
    Assignee: Kyocera Corporation
    Inventors: Katsura Hayashi, Akihiko Nishimoto, Yukihiro Hiramatsu, Yuji Iino, Shuichi Tateno, Riichi Sasamori, Shigeaki Fukumoto