Patents by Inventor Riichiro Takemura
Riichiro Takemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110194361Abstract: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.Type: ApplicationFiled: October 5, 2009Publication date: August 11, 2011Inventors: Takayuki Kawahara, Riichiro Takemura, Kazuo Ono
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Patent number: 7995405Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: GrantFiled: December 14, 2010Date of Patent: August 9, 2011Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Publication number: 20110176379Abstract: A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.Type: ApplicationFiled: January 18, 2011Publication date: July 21, 2011Inventors: Shinichi TAKAYAMA, Akira Kotabe, Kazuo Ono, Tomonori Sekiguchi, Yoshimitsu Yanagawa, Riichiro Takemura
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Patent number: 7973582Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks.Type: GrantFiled: September 5, 2008Date of Patent: July 5, 2011Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama, Hiroaki Nakaya
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Patent number: 7969765Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.Type: GrantFiled: October 8, 2008Date of Patent: June 28, 2011Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
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Publication number: 20110103136Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.Type: ApplicationFiled: November 3, 2010Publication date: May 5, 2011Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
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Publication number: 20110101297Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicant: Renesas Electronics CorporationInventors: Masahiro MONIWA, Nozomu Matsuzaki, Riichiro Takemura
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Patent number: 7933141Abstract: In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.Type: GrantFiled: April 1, 2009Date of Patent: April 26, 2011Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Tomonori Sekiguchi, Riichiro Takemura, Yasutoshi Yamada
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Publication number: 20110079858Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: ApplicationFiled: December 14, 2010Publication date: April 7, 2011Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Patent number: 7903449Abstract: A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.Type: GrantFiled: June 16, 2009Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Tomonori Sekiguchi, Riichiro Takemura, Yasutoshi Yamada
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Patent number: 7903492Abstract: Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command.Type: GrantFiled: December 17, 2008Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama, Hiroaki Nakaya
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Publication number: 20110044092Abstract: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.Type: ApplicationFiled: October 30, 2010Publication date: February 24, 2011Inventors: KAZUO ONO, Riichiro Takemura, Tomonori Sekiguchi
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Patent number: 7884348Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.Type: GrantFiled: April 5, 2010Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventors: Masahiro Moniwa, Nozomu Matsuzaki, Riichiro Takemura
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Patent number: 7876627Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: GrantFiled: January 3, 2008Date of Patent: January 25, 2011Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Patent number: 7859889Abstract: In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.Type: GrantFiled: August 5, 2008Date of Patent: December 28, 2010Assignee: Renesas Electronics CorporationInventors: Norifumi Kameshiro, Riichiro Takemura, Tomoyuki Ishii
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Patent number: 7848177Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.Type: GrantFiled: November 12, 2008Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Shinya Kajiyama, Yutaka Shinagawa, Makoto Mizuno, Hideo Kasai, Takao Watanabe, Riichiro Takemura, Tomonori Sekiguchi
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Patent number: 7843250Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.Type: GrantFiled: January 13, 2010Date of Patent: November 30, 2010Assignee: Hitachi, Ltd.Inventors: Hiroaki Nakaya, Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura
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Patent number: 7843751Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.Type: GrantFiled: January 12, 2009Date of Patent: November 30, 2010Assignee: Hitachi, LtdInventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
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Patent number: 7835171Abstract: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.Type: GrantFiled: July 11, 2008Date of Patent: November 16, 2010Assignee: Hitachi, Ltd.Inventors: Kazuo Ono, Riichiro Takemura, Tomonori Sekiguchi
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Patent number: 7829930Abstract: A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal.Type: GrantFiled: July 9, 2008Date of Patent: November 9, 2010Assignee: Hitachi, Ltd.Inventors: Motoyasu Terao, Hideyuki Matsuoka, Naohiko Irie, Yoshitaka Sasago, Riichiro Takemura, Norikatsu Takaura