Abstract: A data transmission system in which data read out of a first memory is transmitted to a second memory, includes a data buffer for temporarily storing data to be transmitted from the second memory, an identifying module for identifying a maximum permissible transmission unit defined by a bus/address boundary rule for addresses of the second memory, a deciding module for deciding a transmission unit of data to be transmitted to the second memory based on an amount of data which should be transmitted but has not yet been transmitted and the maximum permissible transmission unit identified by the identifying module, a storing control module for reading data for the transmission unit decided by the deciding module out of the first memory starting from data stored at an identified address of the first memory, in accordance with the bus/address boundary rule for the address of the first memory, and for storing the data in the data buffer, and a transmission control module for transmitting a batch of data stored in t

Abstract: A channel switching controller is applied to a communication network such as an ISDN. The network has a first information processor, an exchange, and a second information processor. The channel switching controller easily and speedily switches channels from one to another when a communication error occurs in the network. If communication between the first and second information processors fails, the first information processor notifies the exchange that a communication channel, terminal, or line (telephone number) that is presently being used will be switched to another. In response to the notification, the exchange holds the current call. The first information processor resumes communication through the newly selected communication channel, terminal, or line (telephone number), and the exchange releases the call, to continue the communication between the first and second information processors.

Abstract: A data transfer apparatus which includes data devices which access a common, shared memory. Each data device is connected to a corresponding data buffer. A memory bus is connected to each of the data buffers and to the shared memory to allow data to be transferred between the data buffers and between the data devices and the shared memory via the data buffers. Data is transferrable between a transferring data device to a receiving data device by transferring data from the transferring data device to the data buffer corresponding to the transferring data device, from the data buffer corresponding to the transferring data device to the memory bus, from the memory bus to the data buffer corresponding to the receiving data device, and then from the data buffer corresponding to the receiving data device to the receiving data device.