Patents by Inventor Riley W. Jackson
Riley W. Jackson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10078363Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.Type: GrantFiled: January 15, 2016Date of Patent: September 18, 2018Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
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Publication number: 20160132101Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: ApplicationFiled: January 15, 2016Publication date: May 12, 2016Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
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Patent number: 9305562Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: GrantFiled: April 20, 2015Date of Patent: April 5, 2016Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
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Publication number: 20150228290Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
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Patent number: 9015511Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: GrantFiled: August 27, 2013Date of Patent: April 21, 2015Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
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Publication number: 20130346664Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Patent number: 8522063Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: GrantFiled: April 24, 2012Date of Patent: August 27, 2013Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Publication number: 20120210036Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: ApplicationFiled: April 24, 2012Publication date: August 16, 2012Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Patent number: 8166325Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: GrantFiled: September 22, 2008Date of Patent: April 24, 2012Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Patent number: 7590101Abstract: A computer includes a wireless personal area network (WPAN) interface, a wireless local area network (WLAN) interface and a wireless wide area network (WWAN) interface. A device communicating with the wireless personal area network can command the computer to perform actions using the wireless local area network interface or wireless wide area network interface.Type: GrantFiled: March 31, 2004Date of Patent: September 15, 2009Assignee: Intel CorporationInventors: Richard A. Forand, Riley W. Jackson, James P. Kardach
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Publication number: 20090019185Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: ApplicationFiled: September 22, 2008Publication date: January 15, 2009Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Patent number: 7428650Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.Type: GrantFiled: May 15, 2006Date of Patent: September 23, 2008Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Patent number: 7421597Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.Type: GrantFiled: October 28, 2005Date of Patent: September 2, 2008Assignee: Intel CorporationInventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
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Patent number: 7406610Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.Type: GrantFiled: October 28, 2005Date of Patent: July 29, 2008Assignee: Intel CorporationInventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
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Patent number: 7114090Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.Type: GrantFiled: February 14, 2003Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
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Patent number: 7080271Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.Type: GrantFiled: February 14, 2003Date of Patent: July 18, 2006Assignee: Intel CorporationInventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
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Publication number: 20040163005Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.Type: ApplicationFiled: February 14, 2003Publication date: August 19, 2004Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
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Publication number: 20040162922Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an 110 unit that is coupled to both the I/O unit interface and the controller.Type: ApplicationFiled: February 14, 2003Publication date: August 19, 2004Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty