Abstract: Some embodiments relate to an active pixel for use in a digital pixel sensor (DPS) imaging system having complete intra-pixel charge transfer functionality. The active pixel may include a first photodiode, and a first transfer gate and a second transfer gate each operatively coupled to the first photodiode. The first transfer gate and the second transfer gate may reside at opposite sides of the first photodiode. An electron drift current within the first photodiode may cause two direction charge transfer of charge of the first photodiode to the first transfer gate and the second transfer gate.

Abstract: Some embodiments relate to an imaging system including an active pixel a comparator, a write control circuit, and an analog-to-digital conversion (ADC) memory. The active pixel may include a photodiode and a plurality of transistors. The comparator may be operative coupled to the active pixel and configured to receive an output of the active pixel. The write control circuit may be operative coupled to the comparator and configured to receive an output from the comparator. The ADC memory may be operatively coupled to the write control circuit. A data structure may be stored in the ADC memory, and may be configured to store at least a first data string, which may include a set of flag bits for identifying each ADC operation performed and a set of ADC data bits.

Abstract: Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.

Abstract: A power supply apparatus supplies a power supply voltage VDD. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal VS that corresponds to the power supply voltage VDD. The compensation circuit has input/output characteristics fIO that correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current iCOMP that corresponds to the detection signal VS to or otherwise from a node for generating the power supply voltage VDD.

Abstract: A power supply apparatus supplies a power supply voltage VDD. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal VS that corresponds to the power supply voltage VDD. The compensation circuit has input/output characteristics fIO that correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current iCOMP that corresponds to the detection signal VS to or otherwise from a node for generating the power supply voltage VDD.

Abstract: A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite gate 251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.

Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.

Abstract: This invention describes a unique high-speed implementation for overflow detection logic to be used in high performance shifter functions. The overflow logic makes use of parallelism in combining shift value decoding and mask generation logic with the logic necessary to propagate data. Designs for both 16-bit and 32-bit shifters are presented and performance improvement of the new designs over conventional overflow detection circuits is demonstrated.

Abstract: A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite gate 251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.

Abstract: This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2.

Abstract: The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2.

Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.