Abstract: A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.

Abstract: A timing based adaptive equalization circuit (10) dynamically monitors a signal received at an input terminal (16) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit (26) centers the transition of the equalized signal in a delay line circuit (31). An analog delay locked loop circuit (29) provides a fixed throughput time for matching delay elements of delay line circuits (31, 41 and 51) in the adaptive equalization circuit (10). Timing signals propagating in the delay line circuits (31, 41 and 51) are stored in sampler circuits (36, 46 and 56). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits (46 and 56).

Abstract: A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.

Abstract: A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.

Abstract: A digital BiCMOS memory chip includes a row of memory cells, and an addressing circuit for the row of cells. Each of the memory cells is constructed of field-effect transistors which operate at CMOS voltage levels, whereas the address decorder is constructed of bipolar transistors which operate at ECL voltage levels. A direct connection is made via a row line from the address decoder to the row of memory cells with no ECL-to-CMOS voltage level converter lying there between. This direct connection is made operable by properly selecting all voltages that occur on certain nodes in the address decoder and the memory cell. And, it enables the memory to be read faster plus occupy less chip space and dissipate less power than the prior art.

Abstract: A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set a reset nodes. Also in each cell, a first P-channel transistor couples a first select line to the set node; a first bipolar transistor couples the set node to a first bit line; a second P-channel trnasistor couples a second select line to the reset node; and a second bipolar transistor couples the reset node to a second bit line. Data is read from one port of the cell by pulling up just the set node via the first selected line and first P-channel transistor; and data is read from another port of the cell by pulling up just the reset node via the second select line and second P-channel transistor. Both such reads are fast since the parasitic capacitance of each select line is dependent on just a single pull-up transistor per cell. Also the cell is small in size since it is made with two less transistors than a conventional cell.