Patents by Inventor Rimvydas Mickevicius
Rimvydas Mickevicius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11348017Abstract: Embodiments provide efficient, robust, and accurate programmatic prediction of optimized TCAD simulator system settings for future simulation executions to be performed by a TCAD simulation system.Type: GrantFiled: November 7, 2018Date of Patent: May 31, 2022Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 11152313Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.Type: GrantFiled: July 30, 2019Date of Patent: October 19, 2021Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Rimvydas Mickevicius
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Patent number: 10777638Abstract: Roughly described, an integrated circuit device includes a semiconductor having an overall length. In successively adjacent longitudinal sequence, the semiconductor includes first, second and third lengths all having a same first conductivity type. One end of the longitudinal sequence (the end adjacent to the first length) can be referred to a source end of the sequence, and the other end (adjacent to the third length) can be referred to as a drain end. Overlying the second length is a first gate conductor, which defines a first body region. Overlying a cascode portion of the third length is a second gate conductor, which defines a second body region. The second gate conductor preferably is longitudinally continuous with the first gate conductor, but if not, then the two are connected together by other conductors. The first body region is recessed relative to the first and third lengths of the semiconductor.Type: GrantFiled: January 3, 2019Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 10769339Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ? ( F ˜ 1 , C ? 2 ? q ? E g ? N n ? e ? t ? ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant.Type: GrantFiled: August 8, 2019Date of Patent: September 8, 2020Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Rimvydas Mickevicius
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Patent number: 10733348Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.Type: GrantFiled: June 21, 2018Date of Patent: August 4, 2020Assignee: SYNOPSYS, INC.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 10644107Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed herein is a normally-off, gallium oxide field-effect transistor. The field-effect transistor comprises a source, a source spacer, a first channel region, a second channel region, a drain spacer, and a drain. The source, the source spacer, the first channel region, the second channel region, the drain spacer, and the drain are of a first conductivity type. All the regions have the same type of doping. The field-effect transistor further includes a gate dielectric over the channel body and a gate over the gate dielectric. The first channel region has a cross-sectional area that is smaller than the second channel region.Type: GrantFiled: August 14, 2018Date of Patent: May 5, 2020Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 10403625Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.Type: GrantFiled: October 12, 2018Date of Patent: September 3, 2019Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Publication number: 20190148371Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.Type: ApplicationFiled: October 12, 2018Publication date: May 16, 2019Applicant: Synopsys, Inc.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 10128232Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.Type: GrantFiled: May 19, 2017Date of Patent: November 13, 2018Assignee: SYNOPSYS, INC.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Publication number: 20180300443Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.Type: ApplicationFiled: June 21, 2018Publication date: October 18, 2018Applicant: SYNOPSYS, INC.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 9837523Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.Type: GrantFiled: April 13, 2016Date of Patent: December 5, 2017Assignee: Synopsys, Inc.Inventors: Hiu Y. Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Publication number: 20170338224Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.Type: ApplicationFiled: May 19, 2017Publication date: November 23, 2017Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Publication number: 20170186860Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.Type: ApplicationFiled: April 13, 2016Publication date: June 29, 2017Applicant: Synopsys, Inc.Inventors: Hiu Y. Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 5650634Abstract: A submatrix of semiconductor material contains plural electron conduction annels in either or both series and parallel arrangements. Electrons in the channels are confined by the submatrix and a surrounding main matrix provides photon confinement within the submatrix for nonequilibrium phonons which are mutually interchanged between channels. The confinement enhances the efficiency of energy and momentum transfer by means of nonequilibrium phonons. Embodiments of the invention as a transformer, bistable switch, controlled switch and amplifier are disclosed.Type: GrantFiled: September 1, 1995Date of Patent: July 22, 1997Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Vladimir V. Mitin, Viatcheslav Kochelap, Rimvydas Mickevicius, Mitra Dutta, Michael A. Stroscio
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Patent number: 5459334Abstract: A quantum wire embedded in another material or a quantum wire which is free standing. Specifically, the quantum wire structure is fabricated such that a quantum well semiconductor material, for example Gallium Arsenide (GaAS), is embedded in a quantum barrier semiconductor material, for example Aluminum Arsenide (AlAs). Preferably, the entire quantum wire structure is engineered to form multiple subbands and is limited to a low dimensional quantum structure. The dimensions of the quantum wire structure are preferably around 150.times.250 .ANG.. This structure has a negative absolute conductance at a predetermined voltage and temperature. As a result of the resonant behavior of the density of states, the rates of electron scattering in the passive region (acoustic phonon and ionized impurity scattering as well as absorption of optical phonons) decrease dramatically as the electron kinetic energy increases.Type: GrantFiled: September 20, 1994Date of Patent: October 17, 1995Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Mitra Dutta, Michael A. Stroscio, Vladimir V. Mitin, Rimvydas Mickevicius