Patents by Inventor Rinji Sugino
Rinji Sugino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11430689Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.Type: GrantFiled: October 9, 2018Date of Patent: August 30, 2022Assignee: Infineon Technologies LLCInventors: Rinji Sugino, Fei Wang
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Publication number: 20190198611Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.Type: ApplicationFiled: December 19, 2018Publication date: June 27, 2019Applicant: Cypress Semiconductor CorporationInventors: Rinji Sugino, Lei Xue, Ching-Huang LU, Simon S. Chan
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Patent number: 10256137Abstract: An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: November 3, 2017Date of Patent: April 9, 2019Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Publication number: 20190043751Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.Type: ApplicationFiled: October 9, 2018Publication date: February 7, 2019Applicant: Cypress Semiconductor CorporationInventors: Rinji Sugino, Fei Wang
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Publication number: 20180323208Abstract: A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical NV memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical NV memory cell strings double the memory bits of the device.Type: ApplicationFiled: June 27, 2018Publication date: November 8, 2018Applicant: Cypress Semiconductor CorporationInventors: Rinji Sugino, Scott A. Bell, Lei Xue
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Patent number: 10020317Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.Type: GrantFiled: March 23, 2016Date of Patent: July 10, 2018Assignee: Cypress Semiconductor CorporationInventors: Renhua Zhang, Lei Xue, Rinji Sugino, Krishnaswamy Ramkumar
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Publication number: 20180166323Abstract: A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: ApplicationFiled: November 3, 2017Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventors: Ching-Huang LU, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Patent number: 9831114Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: June 24, 2016Date of Patent: November 28, 2017Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Rinji Sugino, Simon Siu-Sing Chan
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Publication number: 20170263623Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.Type: ApplicationFiled: March 23, 2016Publication date: September 14, 2017Inventors: Renhua Zhang, Lei Xue, Rinji Sugino, Krishnaswamy Ramkumar
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Publication number: 20170062456Abstract: A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical NV memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical NV memory cell strings double the memory bits of the device.Type: ApplicationFiled: December 11, 2015Publication date: March 2, 2017Inventors: Rinji Sugino, Scott Bell, Lei Xue
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Patent number: 9493874Abstract: A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.Type: GrantFiled: November 15, 2012Date of Patent: November 15, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventor: Rinji Sugino
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Patent number: 9437470Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: October 8, 2013Date of Patent: September 6, 2016Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Publication number: 20160211321Abstract: A system for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) is disclosed herein. An integrated circuit (IC) comprises a substrate, a first device, a second device, and an isolator. The isolator is positioned between first and second device. The isolator comprises one or more cavities. The isolator may be filled with dielectric material.Type: ApplicationFiled: February 1, 2016Publication date: July 21, 2016Inventors: Rinji Sugino, Lei Xue, Ching-Huang LU, Simon Siu-Sing CHAN
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Patent number: 9252221Abstract: A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.Type: GrantFiled: December 30, 2013Date of Patent: February 2, 2016Assignee: Cypress Semiconductor CorporationInventors: Rinji Sugino, Scott Bell, Chun Chen, Shenging Fang
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Patent number: 9252026Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.Type: GrantFiled: March 12, 2014Date of Patent: February 2, 2016Assignee: Cypress Semiconductor CorporationInventors: Rinji Sugino, Lei Xue, Ching-Huang Lu, Simon Chan
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Publication number: 20150262838Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Applicant: Spansion LLCInventors: Rinji Sugino, Lei Xue, Ching-Huang Lu, Simon Chan
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Publication number: 20150187891Abstract: A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: Spansion LLCInventors: Rinji SUGINO, Scott BELL, Chun CHEN, Shenging FANG
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Publication number: 20150097245Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Spansion LLCInventors: Ching-Huang LU, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Patent number: 8987092Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.Type: GrantFiled: April 28, 2008Date of Patent: March 24, 2015Assignee: Spansion LLCInventors: Inkuk Kang, Gang Xue, Shenqing Fang, Rinji Sugino, Yi Ma
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Patent number: 8809936Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.Type: GrantFiled: July 31, 2006Date of Patent: August 19, 2014Assignees: Globalfoundries Inc., Spansion LLCInventors: Lei Xue, Rinji Sugino, YouSeok Suh, Hidehiko Shiraiwa, Meng Ding, Shenqing Fang, Joong Jeon