Abstract: Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches.

Abstract: Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed.

Abstract: Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed.

Abstract: Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches.

Abstract: The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored to have just sufficient drive capacity depending on the potential load which may be determined by examining a configuration information loaded to the circuit arrangement. Tailoring for sufficient drive can be achieved either by varying the size or number of circuit components or by adjusting the threshold voltage of circuit elements, or by doing both. Thereby, power consumption can be reduced when circuit components are driven at loads lower than the worst case load.

Abstract: A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.

Abstract: A clamper circuit (1) receives an input signal (3) from the signal wire being clamped, i.e. the victim wire. The clamper circuit (1) also receives aggressor signals (5, 7) from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire. An output signal (9), for clamping the victim wire, is selectively enabled based on the logic states of the input signal (3) and the aggressor signals (5, 7). In addition to selectively providing a clamping signal, the clamper circuit (1) also has the advantage of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, thereby reducing worst case delay and improving the signal integrity.

Abstract: The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island (30) has a local controller (36) communicating with a global controller (42). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.