Patents by Inventor Ripduman Sohan
Ripduman Sohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11966351Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.Type: GrantFiled: March 11, 2021Date of Patent: April 23, 2024Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
-
Patent number: 11960596Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.Type: GrantFiled: March 11, 2021Date of Patent: April 16, 2024Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
-
Patent number: 11824830Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.Type: GrantFiled: April 30, 2021Date of Patent: November 21, 2023Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
-
Patent number: 11726928Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.Type: GrantFiled: June 24, 2021Date of Patent: August 15, 2023Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
-
Publication number: 20230224261Abstract: A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.Type: ApplicationFiled: January 7, 2022Publication date: July 13, 2023Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN, Stephan DIESTELHORST
-
Patent number: 11689648Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.Type: GrantFiled: March 11, 2021Date of Patent: June 27, 2023Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
-
Publication number: 20220414028Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
-
Publication number: 20220292184Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
-
Publication number: 20220292042Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
-
Publication number: 20220294883Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
-
Publication number: 20210258284Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.Type: ApplicationFiled: April 30, 2021Publication date: August 19, 2021Applicant: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
-
Patent number: 11082364Abstract: A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.Type: GrantFiled: April 25, 2019Date of Patent: August 3, 2021Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
-
Patent number: 11012411Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.Type: GrantFiled: November 5, 2018Date of Patent: May 18, 2021Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
-
Publication number: 20200344180Abstract: A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Applicant: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
-
Publication number: 20200145376Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.Type: ApplicationFiled: November 5, 2018Publication date: May 7, 2020Applicant: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts