Abstract: A phase interpolation receiver for receiving angle modulated radio frequency signals. The receiver comprises mixers for down-converting the received angle modulated signal to lower frequency signals, limiters, interpolation filters, and a demodulator. The mixers down-convert the received RF signal to a low IF intermediate frequency signal. The low IF intermediate frequency signal is limited. After further down-conversion to zero IF, using quadrature mixers, the limited signal is phase interpolated. The intermediate frequency is chosen such that the limited signal comprises an unwanted signal at twice the intermediate frequency that acts as a noise spreading signal for spectrally spreading of quantization noise generated by the limiters, and the cut-off frequency of the interpolation filters is chosen such that the unwanted signal and the spread quantization noise are suppressed.

Abstract: A wireless radio for wireless networking communication systems includes a radio frequency (RF) transceiver integrated circuit (IC) and a baseband digital signal processing (DSP) IC. A bidirectional serial digital interface couples data between the RF transceiver IC and the DSP IC to provide a high data rate and low noise. The bidirectional serial digital interface includes a first serial data connection and a second serial data connection. In one embodiment, the RF transceiver IC has a single bit sigma delta A/D modulator to convert an analog signal into a first serial digital bit stream for communication over the first serial data connection. In one embodiment, the DSP IC has a single bit sigma delta digital modulator to generate a second serial digital bit stream for communication over the second serial data connection.

Abstract: This invention describes how to quickly cancel DC offsets that are present in the two quadrature paths of a zero intermediate frequency transceiver. Previously known techniques are not suitable for the 5 GHz WLAN standards because of the very short transmit to receive turn around times and extraordinarily large dc offsets in these systems. This invention solves the above problems. The present invention uses both AC and DC coupling along with automatic gain control techniques to remove unwanted DC offsets within an acceptable time period. The invention further uses a digital signal processor to estimate and subtract out the DC offset errors using time averaged signals. The digital signal processing circuit is capable of further AC filtering and Analog to Digital conversions.

Abstract: In a transceiver comprising a time-division-duplex (TDD) of transmit and receive functions, the characteristics of unwanted image signal energy being transmitted from the transceiver are determined, and thereafter feedback is provided to the transmitter to reduce this unwanted image signal energy. The image signal energy is measured by the receiver component of the transceiver and fed back to the transmitter component of the transceiver. The transmitter component uses the fed back information to adjust the gain and or phase relationship between the quadrature signals that are subsequently quadrature-phase modulated and transmitted. A variety of techniques can be employed to allow the image signal energy to be measured directly by the receiver component. The phase modulation signals at the transmitter can be interchanged, so that the unwanted image signal energy is transmitted in the sideband of the intended signal.

Abstract: A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

Abstract: A transmitter for transmitting a high frequency transmit signal generates a low intermediate frequency quadrature signal, and up-converts the low intermediate frequency quadrature signal to the high frequency transmit signal. The frequency spectrum of the high frequency transmit signal has a transmit band and a sideband corresponding to the transmit band. The transmit band is confined to a total transmit band outside of which severe sideband filtering requirements.apply. Before up-converting, the transmitter provides that the sideband falls at a side of the transmit band such that the sideband falls within the total transmit band.

Abstract: A receiver is calibrated. First, it is ensured that an input of the receiver does not receive useful signals. Thereafter, quadrature output signals of the receiver are correlated and a relative phase of quadrature local oscillators signals, which are used to down-convert received signals, is set at a value corresponding to a minimum correlation value.

Abstract: A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

Abstract: In a transceiver comprising a time-division-duplex (TDD) of transmit and receive functions, the characteristics of unwanted image signal energy being transmitted from the transceiver are determined, and thereafter feedback is provided to the transmitter to reduce this unwanted image signal energy. The image signal energy is measured by the receiver component of the transceiver and fed back to the transmitter component of the transceiver. The transmitter component uses the fed back information to adjust the gain and or phase relationship between the quadrature signals that are subsequently quadrature-phase modulated and transmitted. A variety of techniques can be employed to allow the image signal energy to be measured directly by the receiver component. The phase modulation signals at the transmitter can be interchanged, so that the unwanted image signal energy is transmitted in the sideband of the intended signal.

Abstract: Analog correlation techniques are used in a digital receiver portion of a spread spectrum transceiver to determine when to turn ON given digital receiver components. According to a particular embodiment, an analog correlator receives the down-converted in-phase and quadrature-phase outputs from the radio section and determines when a received signal is coming up at or near a given noise level. A control circuit is coupled to the correlator to selectively activate flash A/D converters in the digital receiver portion of the baseband processor. The analog correlator replaces the RSSI for “sniffing” whether a received signal is present.

Abstract: A quadrature tranceiver has a transmitter, a receiver, and a common local oscillator. With the transmitter switched off and the receiver switched on, a DC-error in the receiver is nulled in servo loops in in-phase and a quadrature receiver paths. After settling, the servo loops provide output values that are freed of the DC-error. DC-nulling output values are then sampled and stored. After sampling, the servo loops are opened. Thereafter, the transmitter is switched on while inputting a fixed signal to the transmitter, and DC-signals injected into in-phase and quadrature paths of the transmitter are adjusted until the opened servo loops provide the same output signal as obtained at the end of the DC-nulling. Corresponding values of the injected DC-signals are then stored as transmitter calibration values.

Abstract: A digital radio device having a quadrature demodulator that does not suffer from substantial amplitude roll-off at the relevant operating range. Such a device is obtained by a phase shifting network in a quadrature branch of the demodulator having a series arrangement of a resistor and an capacitor coupled to an inductor coupled to ground. A junction between the series arrangement and the inductor forms the output of the quadrature branch. Alternative embodiments are provided. The demodulator avoids asymmetric digital signal distortion which can have deteriorating effects, in particular to GFSK-signals or &pgr;/4-DQPSK signals, or the like, and further noise shift of data which is of particular importance in low [S/N]-systems such as paging systems.

Abstract: The present invention offers a low cost, reliable, on chip implementation that takes advantage of circuitry already present in receivers to calibrate and correct for gain and phase errors in a transceiver device. The present invention employs a digital signal processor along with multiple phase shifters and all pass networks to ensure proper levels of quadrature signals within the transceiver. An internally generated double sideband suppressed carrier signal is created to produce the calibration signals used by the digital signal processor.

Abstract: The present invention offers a low cost, reliable, on chip implementation that takes advantage of circuitry already present in receivers to calibrate and correct for gain and phase errors in a transciever device. The present invention employs a digital signal processor along with multiple phase shifters and all pass networks to ensure proper levels of quadrature signals within the transciever. An internally generated double sideband suppressed carrier signal is created to produce the calibration signals used by the digital signal processor.

Abstract: The present invention offers a low cost, reliable, on chip implementation that takes advantage of circuitry already present in receivers to produce a calibration tone used in quadrature signal imbalance adjustments. The present invention employs multiple phase shifters and a double sideband suppressed carrier to produce calibration signals.

Abstract: A zero intermediate frequency radio device has an antenna for receiving a radio frequency signal, and a frequency down converter for down converting the received radio frequency signal to a zero intermediate frequency signal. The radio device further has controllable amplifier stages, controllable AC-coupling stages, controllable filter stages, and a received signal strength indicator. A signal resolving range of the received signal strength indicator is below a high dynamic range of the received radio frequency signal. The radio device further has an automatic gain controller. The automatic gain controller initially sets the gain of the Rx path of the radio device to a maximum of minimum gain, and then waits for DC-offsets in the Rx path to cancel. If, at maximum or minimum gain, a reading of the received signal strength indicator is within a particular range, the automatic gain controller sets the gain to the reading. Then, automatic gain control settles.

Abstract: A CDMA reverse link has a system for providing compensation for phase errors caused by clock jitter in a CDMA reverse link. After filtering, data spread by a pilot PN sequence is supplied to a shift register that produces several data samples for sequential cycles of an internal clock. A memory stores compensation factors representing the clock jitter, pre-calculated for each of the internal clock cycles. A counter counts the internal clock cycles to provide the memory with an address signal indicating a memory location that stores the compensation factor for a current internal clock cycle. Based on the data samples and the compensation factor, an interpolator performs an interpolation algorithm to determine an adjusted spread data value that compensates for phase errors caused by jitter in the internal clock.

Abstract: An approach for converting an M-bit digital input value into an analog output signal involves separately processing the (M−N) number of most significant bits and the N number of least significant bits of the M-bit digital input value. The N number of least significant bits are converted by a pulse density modulator into a pulse density modulated signal. The pulse density modulated signal is processed by a filter to provide a first analog signal. The (M−N) number of most significant bits are processed by a static digital-to-analog converter to provide a second analog signal. The first and second analog signals are combined to provide the analog output signal.

Abstract: An approach for providing image rejection during signal down conversion involves phase shifting quadrature signals at a frequency other than the down converted center frequency. One or more phase shifters coupled to a summer/subtractor provide forty five (45) degrees and one hundred thirty five (135) degrees of phase shift with respect to two quadrature input signals. The one or more phase shifters perform the phase shifts of the quadrature input signals at a frequency other than the center frequency of the down-converted signal.

Abstract: A quadrature modulator with set-and-forget carrier leakage compensation. The quadrature modulator comprises an in-phase and a quadrature branch. In the in-phase and quadrature branches, real-time digital signals are converted to analog signals, the analog signals are filtered, and the filtered analog signals are modulated with a carrier signal and a ninety degrees phase shifted version of the carrier, respectively. The modulated in-phase and quadrature signals are added so as to form a quadrature amplitude modulated signal. Preferably upon powering up of the quadrature modulator, in the in-phase and quadrature branches, carrier leakage is measured. The measured carrier leakage is supplied to comparators, which toggle, when carrier leakage is minimal in the respective in-phase and quadrature branches.