Patents by Inventor Rishubh Khurana
Rishubh Khurana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936395Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.Type: GrantFiled: January 27, 2022Date of Patent: March 19, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
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Publication number: 20230254003Abstract: Certain aspects of the present disclosure provide techniques and apparatus for calibrating radio frequency (RF) circuits using machine learning. One example method generally includes calibrating a first subset of RF circuit calibration parameters. Values are predicted for a second subset of RF circuit calibration parameters based on a machine learning model and the first subset of RF circuit calibration parameters. The second subset of RF circuit calibration parameters may be distinct from the first subset of RF circuit calibration parameters. At least the first subset of RF circuit calibration parameters is verified, and after the verifying, at least the first subset of RF circuit calibration parameters are written to a memory associated with the RF circuit.Type: ApplicationFiled: March 22, 2023Publication date: August 10, 2023Inventors: Lindsey Makana KOSTAS, Rishubh KHURANA, Ahmed YOUSSEF, Francisco LEDESMA, Sergey MURASHOV, Viral RANPARA, Enrique DE LA ROSA, Ming LEUNG, Gurkanwal Singh SAHOTA, Shahnaz SHIRAZI
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Publication number: 20230238972Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.Type: ApplicationFiled: January 27, 2022Publication date: July 27, 2023Inventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
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Publication number: 20230238973Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.Type: ApplicationFiled: January 27, 2022Publication date: July 27, 2023Inventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
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Patent number: 11637582Abstract: Certain aspects of the present disclosure provide techniques and apparatus for calibrating radio frequency (RF) circuits using machine learning. One example method generally includes calibrating a first subset of RF circuit calibration parameters. Values are predicted for a second subset of RF circuit calibration parameters based on a machine learning model and the first subset of RF circuit calibration parameters. The second subset of RF circuit calibration parameters may be distinct from the first subset of RF circuit calibration parameters. At least the first subset of RF circuit calibration parameters is verified, and after the verifying, at least the first subset of RF circuit calibration parameters are written to a memory associated with the RF circuit.Type: GrantFiled: February 8, 2022Date of Patent: April 25, 2023Assignee: QUALCOMM IncorporatedInventors: Lindsey Makana Kostas, Rishubh Khurana, Ahmed Youssef, Francisco Ledesma, Sergey Murashov, Viral Ranpara, Enrique De La Rosa, Ming Leung, Gurkanwal Singh Sahota, Shahnaz Shirazi
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Publication number: 20210194479Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: Rishubh KHURANA, Tanmay NEEMA, Kanak Chandra DAS, Atul Kumar AGRAWAL
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Patent number: 10972092Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.Type: GrantFiled: May 21, 2020Date of Patent: April 6, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rishubh Khurana, Tanmay Neema, Kanak Chandra Das, Atul Kumar Agrawal
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Publication number: 20210036701Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.Type: ApplicationFiled: May 21, 2020Publication date: February 4, 2021Inventors: Rishubh KHURANA, Tanmay NEEMA, Kanak Chandra DAS, Atul Kumar AGRAWAL
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Publication number: 20160191072Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.Type: ApplicationFiled: December 31, 2014Publication date: June 30, 2016Inventors: Shakti Shankar Rath, Rishubh Khurana, Vineet Mishra
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Patent number: 9362939Abstract: Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom.Type: GrantFiled: December 31, 2014Date of Patent: June 7, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shakti Shankar Rath, Rishubh Khurana, Vineet Mishra
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Patent number: 8791845Abstract: A pipeline ADC (analog-to-digital converter) (14) includes a residue amplifier (7) for applying a first residue signal (Vres1) to a first input of a residue amplifier (11A) and to an input of a sub-ADC (8) for resolving a predetermined number (m) of bits and producing a redundancy bit in response to the first residue signal. A level-shifting MDAC (9A) converts the predetermined number of bits and the redundancy bit to an analog signal (10) on the a second input of the residue amplifier, which amplifies the difference between the first residue signal and the analog signal to generate a second residue signal (Vres2). The MDAC causes the residue amplifier to shift the second residue signal back within a predetermined voltage range (±Vref/2) by the end of the amplifying if the second residue signal is outside of the predetermined voltage range.Type: GrantFiled: August 31, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Gautam S. Nandi, Rishubh Khurana
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Publication number: 20140062736Abstract: A pipeline ADC (analog-to-digital converter) (14) includes a residue amplifier (7) for applying a first residue signal (Vres1) to a first input of a residue amplifier (11A) and to an input of a sub-ADC (8) for resolving a predetermined number (m) of bits and producing a redundancy bit in response to the first residue signal. A level-shifting MDAC (9A) converts the predetermined number of bits and the redundancy bit to an analog signal (10) on the a second input of the residue amplifier, which amplifies the difference between the first residue signal and the analog signal to generate a second residue signal (Vres2). The MDAC causes the residue amplifier to shift the second residue signal back within a predetermined voltage range (±Vref/2) by the end of the amplifying if the second residue signal is outside of the predetermined voltage range.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gautam S. Nandi, Rishubh Khurana