Patents by Inventor Rita J. Klein
Rita J. Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100144144Abstract: An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An optional buffering agent may also be included in the composition. The composition may be used to deposit cobalt metal in or on semiconductor substrate surfaces including vias, trenches, and interconnects.Type: ApplicationFiled: February 16, 2010Publication date: June 10, 2010Inventors: Rita J. Klein, Adam J. Regner, III
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Patent number: 7700485Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: October 15, 2007Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventor: Rita J. Klein
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Patent number: 7686874Abstract: An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An optional buffering agent may also be included in the composition. The composition may be used to deposit cobalt metal in or on semiconductor substrate surfaces including vias, trenches, and interconnects.Type: GrantFiled: June 28, 2005Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventors: Rita J. Klein, Adam J. Regner, III
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Patent number: 7666776Abstract: The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the conductive surfaces, consist essentially of tantalum at an uppermost portion, and have a TaN/Ta gradient extending between the lowermost and uppermost portions. Alternatively, the gradient-containing material can have a Co/W gradient extending therethrough. Conductive structures can be formed over the gradient-containing material. The invention also includes constructions comprising electrically conductive lines over a material having a TaN/Ta gradient, or a W/Co gradient, extending therethrough.Type: GrantFiled: September 1, 2005Date of Patent: February 23, 2010Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Rita J. Klein, James E. Green
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Patent number: 7550380Abstract: A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.Type: GrantFiled: January 29, 2007Date of Patent: June 23, 2009Assignee: Micron Technology, Inc.Inventors: Patricia C. Elkins, John T. Moore, Rita J. Klein
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Patent number: 7446415Abstract: Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the area to be plated (e.g., the base of the opening), and a conductive material is electroless plated onto the nucleation layer to fill the opening. The process achieves substantially simultaneous filling of openings having different surface potentials at an about even rate.Type: GrantFiled: March 9, 2005Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventors: Dale W Collins, Rita J Klein
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Patent number: 7375014Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7348234Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7344977Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Publication number: 20080041725Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.Type: ApplicationFiled: August 21, 2006Publication date: February 21, 2008Applicant: Micron Technology, Inc.Inventors: Rita J. Klein, Dale W. Collins, Paul Morgan, Joseph N. Greeley, Nishant Sinha
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Patent number: 7303939Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: October 9, 2003Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventor: Rita J. Klein
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Patent number: 7282131Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7282387Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: November 2, 2005Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventor: Rita J. Klein
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Patent number: 7273778Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7264988Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: November 2, 2005Date of Patent: September 4, 2007Assignee: Micron Technology, Inc.Inventor: Rita J. Klein
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Patent number: 7244678Abstract: A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a complexing agent.Type: GrantFiled: March 16, 2005Date of Patent: July 17, 2007Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, Rita J. Klein
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Patent number: 7189626Abstract: A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a condType: GrantFiled: November 3, 2004Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventors: Patricia C. Elkins, John T. Moore, Rita J. Klein
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Patent number: 7179716Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: February 20, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7179361Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: February 20, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7109056Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: September 20, 2001Date of Patent: September 19, 2006Assignee: Micron Technology, Inc.Inventor: Rita J. Klein