Patents by Inventor Ritchie J. Peachey

Ritchie J. Peachey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9864633
    Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Deepak Mital, Joseph A. Manzella, Ritchie J. Peachey, William Burroughs
  • Publication number: 20150331718
    Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Deepak Mital, Joseph A. Manzella, Ritchie J. Peachey, William Burroughs
  • Patent number: 9094219
    Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Deepak Mital, Joseph A. Manzella, Ritchie J. Peachey, William Burroughs
  • Publication number: 20140254593
    Abstract: An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 11, 2014
    Applicant: LSI CORPORATION
    Inventors: Deepak Mital, Joseph A. Manzella, Ritchie J. Peachey, William Burroughs
  • Patent number: 8705531
    Abstract: An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 22, 2014
    Assignee: LSI Corporation
    Inventors: Joseph A. Manzella, Nilesh S. Vora, Ritchie J. Peachey
  • Publication number: 20120236857
    Abstract: An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Inventors: Joseph A. Manzella, Nilesh S. Vora, Ritchie J. Peachey