Patents by Inventor Ritesh Mittal
Ritesh Mittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230342283Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.Type: ApplicationFiled: June 27, 2023Publication date: October 26, 2023Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
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Patent number: 11726899Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.Type: GrantFiled: November 11, 2021Date of Patent: August 15, 2023Assignee: Synopsys, Inc.Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
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Publication number: 20220066909Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.Type: ApplicationFiled: November 11, 2021Publication date: March 3, 2022Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
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Patent number: 11200149Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.Type: GrantFiled: November 13, 2017Date of Patent: December 14, 2021Assignee: Synopsys, Inc.Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
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Publication number: 20180137031Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.Type: ApplicationFiled: November 13, 2017Publication date: May 17, 2018Inventors: Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
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Publication number: 20140298281Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.Type: ApplicationFiled: October 16, 2013Publication date: October 2, 2014Applicant: Atrenta, Inc.Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
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Patent number: 8846899Abstract: Disclosed are saccharide and phosphocholine derivatives. The derivatives include azide and alkyne derivatives which form one end of a variable length carbon chain. The opposite end of the variable length carbon chain is covalently linked to the saccharide or phosphocholine. The saccharide may be, for instance, a maltoside. The alkyne and azide derivatives of the saccharides and phosphocholine may be reacted together to form amphiphilic molecules useful in cellular membrane studies and applications. By adjusting the length of the carbon chain, the biochemical and biophysical properties of the resultant 1,4-disubstituted 1,2,3-triazole compounds may be custom tailored for the intended application. Resultant molecules may form micelles, bicelle, lipid bilayers and other like structures useful in the isolation and purification of membrane bound or membrane associated proteins and biochemical components.Type: GrantFiled: October 12, 2011Date of Patent: September 30, 2014Assignee: Anatrace Products, LLCInventors: Benjamin R. Travis, Ritesh Mittal, Lijun Huang, Liang Tang
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Patent number: 8839171Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.Type: GrantFiled: October 16, 2013Date of Patent: September 16, 2014Assignee: Atrenta, Inc.Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
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Publication number: 20140200171Abstract: Disclosed are cleaning solutions. More particularly, non-toxic solutions of base, water, alcohol and detergent, that effectively and surprisingly eliminate contaminating aliphatic acids in aqueous solutions. When present as a foam or even a contaminating film remaining on various parts and surfaces, aliphatic acid contaminants can be present a large and costly problem in manufacturing operations, cleaning tasks, personal hygiene. The need to remove such contaminants arises in a myriad environments and situations, such as during the manufacture of detergents, pharmaceuticals, consumer products, coring and core analysis, manipulation of oils, fuels, fermentation applications, manufacture of emollients, moisturizers, liquors, foods such as seafood, milk, butter and other dairy products, water processing, paper products, tissue culture, reusable clinical equipment, and the like.Type: ApplicationFiled: November 14, 2013Publication date: July 17, 2014Inventors: Benjamin R. Travis, Ritesh Mittal, Seth M. Huff, Lijun Huang, Liang Tang
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Patent number: 8609602Abstract: Disclosed are cleaning solutions. More particularly, non-toxic solutions of base, water, alcohol and detergent, that effectively and surprisingly eliminate contaminating aliphatic acids in aqueous solutions. When present as a foam or even a contaminating film remaining on various parts and surfaces, aliphatic acid contaminants can be present a large and costly problem in manufacturing operations, cleaning tasks, personal hygiene. The need to remove such contaminants arises in a myriad environments and situations, such as during the manufacture of detergents, pharmaceuticals, consumer products, coring and core analysis, manipulation of oils, fuels, fermentation applications, manufacture of emollients, moisturizers, liquors, foods such as seafood, milk, butter and other dairy products, water processing, paper products, tissue culture, reusable clinical equipment, and the like.Type: GrantFiled: July 14, 2011Date of Patent: December 17, 2013Assignee: Anatrace Products, LLCInventors: Benjamin R. Travis, Ritesh Mittal, Seth M. Huff, Lijun M. Huang, Liang Tang
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Publication number: 20130096295Abstract: Disclosed are saccharide and phosphocholine derivatives. The derivatives include azide and alkyne derivatives which form one end of a variable length carbon chain. The opposite end of the variable length carbon chain is covalently linked to the saccharide or phosphocholine. The saccharide may be, for instance, a maltoside. The alkyne and azide derivatives of the saccharides and phosphocholine may be reacted together to form amphiphilic molecules useful in cellular membrane studies and applications. By adjusting the length of the carbon chain, the biochemical and biophysical properties of the resultant 1,4-disubstituted 1,2,3-triazole compounds may be custom tailored for the intended application. Resultant molecules may form micelles, bicelle, lipid bilayers and other like structures useful in the isolation and purification of membrane bound or membrane associated proteins and biochemical components.Type: ApplicationFiled: October 12, 2011Publication date: April 18, 2013Applicant: AFFYMETRIX, INC.Inventors: Benjamin R. Travis, Ritesh Mittal, Lijun Huang, Liang Tang
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Publication number: 20120015862Abstract: Disclosed are cleaning solutions. More particularly, non-toxic solutions of base, water, alcohol and detergent, that effectively and surprisingly eliminate contaminating aliphatic acids in aqueous solutions. When present as a foam or even a contaminating film remaining on various parts and surfaces, aliphatic acid contaminants can be present a large and costly problem in manufacturing operations, cleaning tasks, personal hygiene. The need to remove such contaminants arises in a myriad environments and situations, such as during the manufacture of detergents, pharmaceuticals, consumer products, coring and core analysis, manipulation of oils, fuels, fermentation applications, manufacture of emollients, moisturizers, liquors, foods such as seafood, milk, butter and other dairy products, water processing, paper products, tissue culture, reusable clinical equipment, and the like.Type: ApplicationFiled: July 14, 2011Publication date: January 19, 2012Applicant: AFFYMETRIX, INC.Inventors: Benjamin R. Travis, Ritesh Mittal, Seth M. Huff, Lijun M. Huang, Liang Tang
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Patent number: D766272Type: GrantFiled: July 1, 2015Date of Patent: September 13, 2016Assignee: EXLSERVICE HOLDINGS, INC.Inventors: Ritesh Mittal, Benny Abraham, Mahnaz Khezrzadeh