Abstract: An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal, providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

Abstract: An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Abstract: According to the invention, an apparatus and method are disclosed for sensing the contents of non-volatile memory. According to one embodiment, a set of local sensing circuits is used to read the logical values stored in memory cells contained within a partition of a non-volatile memory device.

Abstract: A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.

Abstract: An apparatus and method are disclosed for providing a load for non-volatile memory drain bias. According to one embodiment, a load comprising a column load and a current mirror is referenced using a sample and hold voltage reference.

Abstract: A flash memory using a pre-sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre-sensing amplifier. The differential output is coupled to a bus, which is also coupled to a post-sensing amplifier. The differential configuration on the bus allows marginal voltage differences to be detected by the post-sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage.

Abstract: An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Abstract: A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.

Abstract: An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Abstract: According to the invention, an apparatus and method are disclosed for sensing the contents of non-volatile memory. According to one embodiment, a set of local sensing circuits is used to read the logical values stored in memory cells contained within a partition of a non-volatile memory device.

Abstract: A flash memory using a pre-sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre-sensing amplifier. The differential output is coupled to a bus, which is also coupled to a post-sensing amplifier. The differential configuration on the bus allows marginal voltage differences to be detected by the post-sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage.

Abstract: An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal. providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

Abstract: An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.