Patents by Inventor Ritsuko Kawasaki

Ritsuko Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7179698
    Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: February 20, 2007
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Koichiro Tanaka, Kenji Kasahara, Ritsuko Kawasaki
  • Publication number: 20070034870
    Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.
    Type: Application
    Filed: October 17, 2006
    Publication date: February 15, 2007
    Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
  • Patent number: 7176068
    Abstract: The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: February 13, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Kitakado, Ritsuko Kawasaki, Kenji Kasahara
  • Patent number: 7132687
    Abstract: To improve the operation characteristic and reliability of a semiconductor device by optimizing the structure of bottom gate type or inverted stagger type TFTs arranged in circuits of the semiconductor device in accordance with the function of the respective circuits. At least LDD regions that overlap with a gate electrode are formed in an N channel type TFT of a driving circuit, and LDD regions that do not overlap with the gate electrode are formed in an N channel type TFT of a pixel matrix circuit. The concentration of the two kinds of LDD regions is differently set from each other, to thereby obtain the optimal circuit operation.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: November 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ritsuko Kawasaki, Hidehito Kitakado, Kenji Kasahara, Shunpei Yamazaki
  • Patent number: 7132686
    Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: November 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
  • Publication number: 20060246634
    Abstract: To realize TFT enabling high-speed operation by fabricating a crystalline semiconductor film in which positions and sizes of crystal grains are controlled and using the crystalline semiconductor film in a channel forming region of TFT, a film thickness is stepped by providing a stepped difference in at least one layer of a matrix insulating film among a plurality of matrix insulating films having refractive indices different from each other. By irradiating laser beam from a rear face side of a substrate (or both sides of a surface side and the rear face side of the substrate), there is formed an effective intensity distribution of laser beam with regard to a semiconductor film and there is produced a temperature gradient in correspondence with a shape of the stepped difference and a distribution of the film thickness of the matrix insulating film in the semiconductor film.
    Type: Application
    Filed: June 19, 2006
    Publication date: November 2, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenji Kasahara, Ritsuko Kawasaki, Hisashi Ohtani
  • Patent number: 7129522
    Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 31, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Ritsuko Kawasaki
  • Patent number: 7122409
    Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: October 17, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ritsuko Kawasaki, Kenji Kasahara, Hisashi Ohtani
  • Publication number: 20060163580
    Abstract: To provide a technique required for purifying the interface between an active layer and an insulating film. On a substrate (101), a gate wiring (103) is formed and the surface thereof is covered with a gate oxide film (104). Then, a first insulating film (105a), a second insulating film (105b), a semiconductor film (106) and a protective film (107) are sequentially formed and layered without exposing them to the air. Further, the semiconductor film (106) is irradiated with laser light through the protective film (107). In this way, a TFT may be given good characteristics by completely purifying the interface of the semiconductor film.
    Type: Application
    Filed: April 8, 2002
    Publication date: July 27, 2006
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Ritsuko Kawasaki
  • Patent number: 7064016
    Abstract: To realize TFT enabling high-speed operation by fabricating a crystalline semiconductor film in which positions and sizes of crystal grains are controlled and using the crystalline semiconductor film in a channel forming region of TFT, a film thickness is stepped by providing a stepped difference in at least one layer of a matrix insulating film among a plurality of matrix insulating films having refractive indices different from each other. By irradiating laser beam from a rear face side of a substrate (or both sides of a surface side and the rear face side of the substrate), there is formed an effective intensity distribution of laser beam with regard to a semiconductor film and there is produced a temperature gradient in correspondence with a shape of the stepped difference and a distribution of the film thickness of the matrix insulating film in the semiconductor film.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 20, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenji Kasahara, Ritsuko Kawasaki, Hisashi Ohtani
  • Publication number: 20060113543
    Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 1, 2006
    Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
  • Patent number: 7015505
    Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: March 21, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
  • Patent number: 6974731
    Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: December 13, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Koichiro Tanaka, Kenji Kasahara, Ritsuko Kawasaki
  • Publication number: 20050247685
    Abstract: To form a polycrystalline silicon film having a grain size of 1 ?m or greater by means of laser annealing. A beam emitted from a laser apparatus (101) is split in two by a half mirror. The split beams are processed into linear shapes by cylindrical lenses (102) to (105), and (207), then simultaneously irradiate an irradiation surface (209). If an amorphous silicon film formed on a glass substrate is disposed on the irradiation surface (209), an area will be irradiated by both a linear shape beam entering from a front surface and a linear shape beam that has transmitted through the glass surface. Both linear shape beams irradiate the same area to thereby crystallize the amorphous silicon film.
    Type: Application
    Filed: June 22, 2005
    Publication date: November 10, 2005
    Inventors: Koichiro Tanaka, Shunpei Yamazaki, Ritsuko Kawasaki
  • Patent number: 6927109
    Abstract: To form a polycrystalline silicon film having a grain size of 1 ?m or greater by means of laser annealing. A beam emitted from a laser apparatus (101) is split in two by a half mirror. The split beams are processed into linear shapes by cylindrical lenses (102) to (105), and (207), then simultaneously irradiate an irradiation surface (209). If an amorphous silicon film formed on a glass substrate is disposed on the irradiation surface (209), an area will be irradiated by both a linear shape beam entering from a front surface and a linear shape beam that has transmitted through the glass surface. Both linear shape beams irradiate the same area to thereby crystallize the amorphous silicon film.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: August 9, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Shunpei Yamazaki, Ritsuko Kawasaki
  • Publication number: 20050116225
    Abstract: This invention improves TFT characteristics by making an interface between an active layer, especially a region forming a channel formation region and an insulating film excellent, and provides a semiconductor device provided with a semiconductor circuit made of a semiconductor element having uniform characteristics and a method of fabricating the same. In order to achieve the object, a gate wiring line is formed on a substrate or an under film, a gate insulating film, an initial semiconductor film, and an insulating film are formed into a laminate without exposing them to the atmosphere, and after the initial semiconductor film is crystallized by irradiation of infrared light or ultraviolet light (laser light) through the insulating film, patterning is carried out to obtain an active layer and a protection film each having a desired shape, and then, a resist mask is used to fabricate the semiconductor device provided with an LDD structure.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 2, 2005
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Ritsuko Kawasaki
  • Publication number: 20050051772
    Abstract: To improve the operation characteristic and reliability of a semiconductor device by optimizing the structure of bottom gate type or inverted stagger type TFTs arranged in circuits of the semiconductor device in accordance with the function of the respective circuits. At least LDD regions that overlap with a gate electrode are formed in an N channel type TFT of a driving circuit, and LDD regions that do not overlap with the gate electrode are formed in an N channel type TFT of a pixel matrix circuit. The concentration of the two kinds of LDD regions is differently set from each other, to thereby obtain the optimal circuit operation.
    Type: Application
    Filed: October 5, 2004
    Publication date: March 10, 2005
    Inventors: Ritsuko Kawasaki, Hidehito Kitakado, Kenji Kasahara, Shunpei Yamazaki
  • Patent number: 6844249
    Abstract: The invention relates to a method for manufacturing a semiconductor device, and it is an object of the invention to form a semiconductor area formed in island-like patterns as a single crystal or an area which can be regarded as a single crystal, and to simultaneously achieve a laminated structure by which various characteristics of TFTs can be stabilized, wherein an insulation film is formed on a glass substrate, and island-like semiconductor layer is formed thereon. A laser beam passed through a cylindrical lens is made into a linear laser beam and irradiated onto the island-like semiconductor layer by an optical system.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 18, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ritsuko Kawasaki, Kenji Kasahara, Shunpei Yamazaki
  • Patent number: 6838324
    Abstract: This invention improves TFT characteristics by making an interface between an active layer, especially a region forming a channel formation region and an insulating film excellent, and provides a semiconductor device provided with a semiconductor circuit made of a semiconductor element having uniform characteristics and a method of fabricating the same. In order to achieve the object, a gate wiring line is formed on a substrate or an under film, a gate insulating film, an initial semiconductor film, and an insulating film are formed into a laminate without exposing them to the atmosphere, and after the initial semiconductor film is crystallized by irradiation of infrared light or ultraviolet light (laser light) through the insulating film, patterning is carried out to obtain an active layer and a protection film each having a desired shape, and then, a resist mask is used to fabricate the semiconductor device provided with an LDD structure.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: January 4, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Ritsuko Kawasaki
  • Publication number: 20040248387
    Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.
    Type: Application
    Filed: September 4, 2003
    Publication date: December 9, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ritsuko Kawasaki, Kenji Kasahara, Hisashi Ohtani