Abstract: The present invention relates to a data processing device for mass spectrometry, in which measurements are performed in a high dynamic range without causing an overrange in an A/D converter in any TOF scan. A data acquisition circuit of a mass spectrometer includes an amplitude value computing circuit which measures and stores a maximum amplitude value of an ion detection signal, a gain control circuit for determining and setting a gain amount for the next measurement, and others. From the immediately preceding TOF scan data or TOF scan data plural times before, the maximum amplitude value of the ion detection signal is extracted. Then, before the next TOF scan, an optimum gain amount is determined based on the extracted maximum amplitude value to adjust the gain of the input signal, and the ion signal is sampled in the A/D converter.

Abstract: For the achievement of data transfer time reduction, removal of noise data, and analytical efficiency improvement in an ADC data processing function of a time-of-flight mass spectrometer, the mass spectrometer comprises a data acquisition circuit including: an A/D converter; a signal intensity addition memory that stores data of ion signals such as a time range and the number of measurements and performs an addition process; a voltage value frequency addition memory that performs an addition process of frequencies of voltage values of the predetermined time range and the number of measurements and stores addition results; a threshold level computation circuit that computes a predetermined threshold level from the results in the memory; a compression memory that extracts only data exceeding the threshold level from the data in the signal intensity addition memory; and a counter that controls a measurement time for data acquisition and the operation of each circuit.

Abstract: A magnetic characteristic inspecting apparatus including a plurality of disk rotating devices or a plurality of magnetic heads include a unit for switching output signals of write signal production units or allocating the output signals to the magnetic heads, a unit for switching signals read from the magnetic heads or allocating the read signals to measurement resources, and a unit for selecting any of the disk rotating devices synchronously with which the measurement resources will perform measurement. The write signal production units and measurement resources are shared among inspections of the plurality of disk rotating devices or the plurality of heads.

Abstract: A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+?V) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.

Abstract: A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit.

Abstract: A semiconductor device having a liquid crystal driving circuit is disclosed. The driving circuit includes a digital functional unit and an analog functional unit. The digital functional unit is comprised of a display controller and a display data storage RAM, while the analog functional unit is made up of a gradation voltage generating circuit and a gradation voltage selecting circuit. The digital and analog function units are functionally divided from each other and testing of the digital function and testing of the analog function unit are performed in an overlapping manner independently from each other.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: By means for detecting offsets and gain differentials among signal distribution paths, phase shifts of sampling clocks supplied to a plurality of A/D converters, and frequency-dependence of the transfer function and phase response of signal paths, errors due to these factors are detected. Based on the detected values of these factors and errors, using reference signals, test data errors are compensated.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: In an odd side storage circuit, logical values of a decision subject signal HCMP are stored in first and second FFs respectively at decision edges LH and HL generated from odd-numbered edges of a decision edge EH. Logical values of a delayed decision subject signal HCMP′ are stored in third and fourth FFs. According to a selection signal generated by a selection signal generation circuit based on outputs of the third and fourth FFs, a first selector selects an output of the first or second FF. An even side storage circuit operates similarly at even-numbered edges. A second selector selects the odd and even side storage circuits alternately. The FFs in the odd and even side storage circuits are reset by a decision edge LH′ of the even side and the decision edge HL of the odd side, respectively.

Abstract: An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate.

Abstract: In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating condition, programmed input data set to delay circuits are corrected by a circuit portion for measuring the delay time of a phase shifting adjustment delay circuit with respect to variations in delay time caused by variations in the apparatus operating condition, a first arithmetic operation circuit for calculating the rate of variation on the basis of measured values, and a second arithmetic operation circuit for calculating the quantity of variation on the basis of the rate of variation.

Abstract: In a digital circuitry apparatus in which clock distribution can be performed with high accuracy even in the case where variations in delay time are caused by variations in the apparatus operating condition, programmed input data set to delay circuits are corrected by a circuit portion for measuring the delay time of a phase shifting adjustment delay circuit with respect to variations in delay time caused by variations in the apparatus operating condition, a first arithmetic operation circuit for calculating the rate of variation on the basis of measured values, and a second arithmetic operation circuit for calculating the quantity of variation on the basis of the rate of variation.

Abstract: An object of the present invention is to provide a time interval measurement circuit having especially high time measurement precision and resolution in time interval measurement between two signals and requiring short measurement time. In order to achieve the above described object, a time interval measurement circuit according to the present invention comprises two parallel transmission lines, differential output drivers connected to both ends of said transmission lines, a plurality of potential difference sensing means so disposed between said transmission lines at predetermined intervals as to generate an output signal upon an excess of potential difference between said two transmission lines over a predetermined level, and means for detecting, on the basis of output signals supplied from said potential difference sensing means, which potential difference sensing means has generated an output signal.

Abstract: A wave formatter for generating an output waveform used in a logic circuit testing system is disclosd. The wave formatter includes a data generator for outputting in parallel a plurality of data signals having a polarity and a type in response to a control signal for determining the polarity of the data signals and a control data signal for determining the type of the data signals which are received on external input lines of the data generator in synchronism with a test cycle clock. The data generator decodes the control data signals to produce the plurality of data signals in parallel. A shift data supply is provided which receives the plurality of data signals from the data generator and samples the plurality of data signals to output in parallel data signals in response to the test cycle clock.