Patents by Inventor Ritu Chaba
Ritu Chaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527282Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.Type: GrantFiled: January 7, 2021Date of Patent: December 13, 2022Assignee: QUALCOMM IncorporatedInventors: Changho Jung, Keejong Kim, Chulmin Jung, Ritu Chaba
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Publication number: 20210134358Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.Type: ApplicationFiled: January 7, 2021Publication date: May 6, 2021Inventors: Changho JUNG, Keejong KIM, Chulmin JUNG, Ritu CHABA
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Patent number: 10923185Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.Type: GrantFiled: June 4, 2019Date of Patent: February 16, 2021Assignee: Qualcomm IncorporatedInventors: Changho Jung, Keejong Kim, Chulmin Jung, Ritu Chaba
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Publication number: 20200388328Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.Type: ApplicationFiled: June 4, 2019Publication date: December 10, 2020Inventors: Changho Jung, Keejong Kim, Chulmin Jung, Ritu Chaba
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Patent number: 10622044Abstract: An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.Type: GrantFiled: December 14, 2017Date of Patent: April 14, 2020Assignee: Qualcomm IncorporatedInventors: Bipin Duggal, Naishad Parikh, Ritu Chaba
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Patent number: 10290345Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.Type: GrantFiled: October 21, 2016Date of Patent: May 14, 2019Assignee: QUALCOMM IncorporatedInventors: Arun Babu Pallerla, Ritu Chaba
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Publication number: 20190096460Abstract: An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.Type: ApplicationFiled: December 14, 2017Publication date: March 28, 2019Inventors: Bipin DUGGAL, Naishad PARIKH, Ritu CHABA
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Patent number: 10242720Abstract: A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.Type: GrantFiled: March 25, 2010Date of Patent: March 26, 2019Assignee: QUALCOMM IncorporatedInventors: Nan Chen, Ritu Chaba
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Publication number: 20190035796Abstract: An apparatus includes first means for routing current coupled to a bit cell. The apparatus includes third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus includes second means for routing current. The second means for routing current is between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.Type: ApplicationFiled: October 3, 2018Publication date: January 31, 2019Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
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Patent number: 10141317Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.Type: GrantFiled: November 9, 2016Date of Patent: November 27, 2018Assignee: QUALCOMM IncorporatedInventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
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Patent number: 9916904Abstract: Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.Type: GrantFiled: February 2, 2009Date of Patent: March 13, 2018Assignee: QUALCOMM IncorporatedInventors: Nan Chen, Mehdi Hamidi Sani, Ritu Chaba
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Publication number: 20170278565Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.Type: ApplicationFiled: October 21, 2016Publication date: September 28, 2017Inventors: Arun Babu Pallerla, Ritu Chaba
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Publication number: 20170062439Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.Type: ApplicationFiled: November 9, 2016Publication date: March 2, 2017Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
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Patent number: 9524972Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.Type: GrantFiled: February 12, 2015Date of Patent: December 20, 2016Assignee: Qualcomm IncorporatedInventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
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Patent number: 9514805Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.Type: GrantFiled: March 28, 2016Date of Patent: December 6, 2016Assignee: QUALCOMM IncorporatedInventors: Arun Babu Pallerla, Ritu Chaba
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Publication number: 20160240539Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.Type: ApplicationFiled: February 12, 2015Publication date: August 18, 2016Inventors: Niladri Narayan Mojumder, Ritu Chaba, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
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Patent number: 9418716Abstract: A bit line and word line tracking circuit is provided that accounts for the power-supply-voltage-dependent delays in a memory having a logic power domain powered by a logic power supply voltage and a memory power domain powered by a memory power supply voltage.Type: GrantFiled: July 31, 2015Date of Patent: August 16, 2016Assignee: QUALCOMM IncorporatedInventors: Arun Babu Pallerla, Ritu Chaba
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Publication number: 20150357013Abstract: A memory and a method for operating the memory are provided. The memory includes a bitline and at least one memory cell coupled to the bitline. A bitline precharge circuit is configured to precharge the bitline for a memory access and to deactivate to float the bitline in a standby state. A reference circuit is configured to charge a load circuit to a voltage in the standby state. In one example, the load circuit includes a dummy bitline having a substantially same or greater electrical characteristic of the bitline. The reference circuit includes a dummy bitline precharge circuit configured to charge the dummy bitline to the voltage in the standby state.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Applicant: QUALCOMM IncorporatedInventors: Alex Dongkyu PARK, Venkatasubramanian NARAYANAN, Ritu CHABA, Derek Xiaoxiang YANG, Arun Babu PALLERLA
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Patent number: 9188642Abstract: A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.Type: GrantFiled: August 23, 2013Date of Patent: November 17, 2015Assignee: QUALCOMM IncorporatedInventors: Chirag Gulati, Ritu Chaba, Lakshmikantha Holla Vakwadi
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Patent number: 9111589Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.Type: GrantFiled: September 4, 2013Date of Patent: August 18, 2015Assignee: QUALCOMM IncorporatedInventors: Rakesh Kumar Sinha, Chirag Gulati, Ritu Chaba, Sei Seung Yoon