Patents by Inventor Ritu Shrivastava
Ritu Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11632365Abstract: Various methods, apparatuses/systems, and media for automatically establishing a communication between two or more applications that do not share a compatible authentication model are disclosed. A receiver receives a request from a first application to communicate with a second application, wherein the first application supports a first authentication model and the second application supports a second authentication model which is incompatible with the first authentication model. A processor utilizes a configurable gateway layer, in response to receiving the request, to mediate a communication between the first application and the second application; and routes the request from the first application to the configurable gateway layer. The configurable gateway layer translates the first authentication model to the second authentication model.Type: GrantFiled: May 28, 2021Date of Patent: April 18, 2023Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Kumar Rao Krishnagi, Kevin Carrier, Vineshkumar Dharmalingam, Ritu Shrivastava, Ananth Rajasekaran, Najma Aden, Robert B Grant, Matthew J Porter, Nalini S Boda, Mark Alan Wells, Vijay Kumar Perla, Laxman Dongisharapu
-
Publication number: 20220337576Abstract: Various methods, apparatuses/systems, and media for automatically establishing a communication between two or more applications that do not share a compatible authentication model are disclosed. A receiver receives a request from a first application to communicate with a second application, wherein the first application supports a first authentication model and the second application supports a second authentication model which is incompatible with the first authentication model. A processor utilizes a configurable gateway layer, in response to receiving the request, to mediate a communication between the first application and the second application; and routes the request from the first application to the configurable gateway layer. The configurable gateway layer translates the first authentication model to the second authentication model.Type: ApplicationFiled: May 28, 2021Publication date: October 20, 2022Applicant: JPMorgan Chase Bank, N.A.Inventors: Kumar RAO KRISHNAGI, Kevin CARRIER, Vineshkumar DHARMALINGAM, Ritu SHRIVASTAVA, Ananth RAJASEKARAN, Najma ADEN, Robert B GRANT, Matthew J PORTER, Nalini S BODA, Mark Alan WELLS, Vijay Kumar PERLA, Laxman DONGISHARAPU
-
Patent number: 8395926Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME). The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The layers can be provided in a lateral arrangement, such as an end-to-end, face-to-face, L-shaped or U-shaped arrangement. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element.Type: GrantFiled: June 9, 2011Date of Patent: March 12, 2013Assignee: SanDisk 3D LLCInventors: Franz Kreupl, Ritu Shrivastava
-
Publication number: 20110310654Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME). The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The layers can be provided in a lateral arrangement, such as an end-to-end, face-to-face, L-shaped or U-shaped arrangement. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element.Type: ApplicationFiled: June 9, 2011Publication date: December 22, 2011Inventors: Franz Kreupl, Ritu Shrivastava
-
Patent number: 7799598Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: GrantFiled: March 14, 2008Date of Patent: September 21, 2010Assignee: ZettaCore, Inc.Inventors: Werner G. Kuhr, Ritu Shrivastava, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske
-
Patent number: 7642546Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.Type: GrantFiled: November 30, 2006Date of Patent: January 5, 2010Assignees: Zettacore, Inc., North Carolina State UniversityInventors: Veena Misra, Ritu Shrivastava, Zhong Chen, Guru Mathur
-
Publication number: 20080219041Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: ApplicationFiled: March 14, 2008Publication date: September 11, 2008Inventors: Werner G. Kuhr, Ritu Shrivastava, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske
-
Patent number: 7358113Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: GrantFiled: April 29, 2005Date of Patent: April 15, 2008Assignee: Zettacore, Inc.Inventors: Ritu Shrivastava, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske
-
Publication number: 20070164374Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.Type: ApplicationFiled: November 30, 2006Publication date: July 19, 2007Inventors: Veena Misra, Ritu Shrivastava, Zhong Chen, Guru Mathur
-
Publication number: 20050270822Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.Type: ApplicationFiled: April 29, 2005Publication date: December 8, 2005Inventors: Ritu Shrivastava, Antonio Gallo, Kenneth Mobley, Tom DeBolske
-
Patent number: 6921688Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.Type: GrantFiled: March 7, 2003Date of Patent: July 26, 2005Assignee: Alliance SemiconductorInventor: Ritu Shrivastava
-
Patent number: 6903434Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.Type: GrantFiled: May 20, 1999Date of Patent: June 7, 2005Assignee: Alliance SemiconductorsInventor: Ritu Shrivastava
-
Publication number: 20030151111Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.Type: ApplicationFiled: March 7, 2003Publication date: August 14, 2003Inventor: Ritu Shrivastava
-
Patent number: 6589834Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.Type: GrantFiled: May 3, 2001Date of Patent: July 8, 2003Assignee: Alliance Semiconductor CorporationInventors: Chitranjan N. Reddy, Ritu Shrivastava
-
Patent number: 6472267Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.Type: GrantFiled: December 3, 2001Date of Patent: October 29, 2002Assignee: Alliance Semiconductor CorporationInventors: Ritu Shrivastava, Chitranjan N. Reddy
-
Patent number: 6429076Abstract: A flash EPROM cell (10) is disclosed having increased capacitive coupling between a floating gate (28) and a control gate (32). Vertical structural elements (34a and 34b) are formed on field oxide regions (20) on opposing sides of the flash EPROM cell channel 20, in the channel width direction. The structural elements (34a and 34b) include relatively vertical faces. The floating gate (28) conformally cover the channel 20 and the vertical faces of the structural elements (34a and 34b). The control gate (32) conformally covers the floating gate (28). The vertical displacement introduced by the structural elements (34a and 34b) increases the overlap area between the floating gate (28) and the control gate (32) without increasing the overlap area of the floating gate (28) and the channel 20, resulting in increased capacitive coupling between the control gate (32) and the floating gate (28).Type: GrantFiled: January 22, 2001Date of Patent: August 6, 2002Assignee: Alliance Semiconductor CorporationInventors: Perumal Ratnam, Ritu Shrivastava
-
Publication number: 20020089029Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.Type: ApplicationFiled: May 20, 1999Publication date: July 11, 2002Inventor: RITU SHRIVASTAVA
-
Publication number: 20020081802Abstract: A DRAM device (200) is disclosed having a plurality of memory cells (208) formed on a substrate (202). Each memory cell (208) includes a transistor (210) having a gate (212), and a storage capacitor (214) having a bottom plate (226) covered with a capacitor dielectric (234). A relatively thin top plate (236) is formed over a number of memory cells (208) in a array portion (204) of the DRAM device (200). The top plate (236) extends to a peripheral array portion (206) where contact is made thereto by metallization (248), by way of a plate contact hole (244). An etch stop (240), formed from the same layer as the gate (212) in the preferred embodiment, is disposed in the peripheral array portion (206) below the plate contact hole (244). The etch stop (240) provides greater flexibility in the plate contact hole etching step, by preventing the plate contact hole (244) from extending through the top plate (236) and to the substrate (202).Type: ApplicationFiled: November 7, 2001Publication date: June 27, 2002Inventors: Ritu Shrivastava, Chitranjan N. Reddy
-
Patent number: 6392267Abstract: A flash EPROM array (100) and method of manufacture is disclosed. Source regions (118a-118f) are shared between the memory cells (108a,l-108d,n) of row (104a-104d) pairs, and are isolated from one another in the row direction by isolation regions 120. Low resistance source conductor members (122a-122b) extend in the row direction and are formed over the source regions (118a-118f) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.Type: GrantFiled: April 25, 1997Date of Patent: May 21, 2002Assignee: Alliance Semiconductor CorporationInventors: Ritu Shrivastava, Chitranjan N. Reddy
-
Publication number: 20020053692Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.Type: ApplicationFiled: December 3, 2001Publication date: May 9, 2002Applicant: Alliance Semiconductor CorporationInventors: Ritu Shrivastava, Chitranjan N. Reddy