Abstract: A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.

Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.

Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

Abstract: Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

Abstract: A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.

Abstract: Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.