Patents by Inventor Riza T. CAKICI

Riza T. CAKICI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and circuit for simulating gate-to-drain breakdown
    Patent number: 8554531
    Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Paul E. Nicollian, Riza T. Cakici
  • SYSTEM AND CIRCUIT FOR SIMULATING GATE-TO-DRAIN BREAKDOWN
    Publication number: 20120043619
    Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul E. NICOLLIAN, Riza T. CAKICI