Patents by Inventor Rob Abbott
Rob Abbott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962441Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: GrantFiled: July 25, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Publication number: 20220360476Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 11398933Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: GrantFiled: February 1, 2021Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Publication number: 20220158878Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 11240075Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: GrantFiled: January 25, 2021Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Publication number: 20210218605Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 25, 2021Publication date: July 15, 2021Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Publication number: 20210160107Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 10911272Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: GrantFiled: January 13, 2020Date of Patent: February 2, 2021Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 10904044Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: GrantFiled: January 13, 2020Date of Patent: January 26, 2021Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Publication number: 20200252248Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 13, 2020Publication date: August 6, 2020Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Publication number: 20200252247Abstract: A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.Type: ApplicationFiled: January 13, 2020Publication date: August 6, 2020Inventors: Chaitanya Palusa, Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh
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Patent number: 9716507Abstract: A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.Type: GrantFiled: April 14, 2016Date of Patent: July 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Muhammad Nummer, Rob Abbott